Sun Microsystems, Inc.

Cray Research, Inc.

Celerity Computing

Andrew Jackson McCrocklin

Nicholas E Aneshansley

Daniel P Drogichen

Douglas B Meyer

Patricia Shanahan

James E Kocol

Gary L Riddle

Jeffrey P Anderson

James J Whelan

Eric Cedric Pilmore

Sandra Cecilia Lee

Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.

Multiprocessor computer having configurable hardware system domains

An operating system (OS) of a data processor physically relocates segments of memory containing real addresses used by the operating system itself, which addresses must remain unaltered within the system. The system identifies a memory bank containing a source segment having such real addresses, quiesces the OS, and copies the source segment to a target memory module. A register identifying the real addresses stored in the target module is renamed to the addresses of source segment, and the OS resumes executing normal tasks. The data processing system may have multiple system modules each having processors, memory, and/or other components.

Transparent relocation of real memory addresses in the main memory of a

A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.

Direct-execution microprogrammable microprocessor system

Growing community of inventors

San Diego, CA, United States of America

Andrew Jackson McCrocklin