Cypress Semiconductor Corporation

Netlogic Microsystems, Inc

Simon Fraser University

Waterbit, Inc.

Andrew J Wright

James H Lie

Bartosz Banachowicz

Dinesh Maheshwari

Brenor L Brophy

Anup Nayak

Jeffery Scott Hunt

Christopher W Jones

Steven Holdcroft

Hari Om

Brian P Evans

Timothy James Peckham

Benjamin Britton

James Daniel Merchant

Bin Jiang

Thomas Weissbach

Gordon Carskadon

Srinivasan Venkatachary

Craig Nemecek

Eric H Voelkel

William Koutny

Rochan Sankar

Manu Pillai

Ashok Kumar

Ramesh Chettuvetty

Jonathan William Ward

Sonal Chandrasekharan

Jiantao Fan

Hiromu Takehara

Tushar Kachhdiya

Leif Chastaine

Provided herein are imidazolium polymers having steric hindrance at the 4-position of the imidazole moieties in the polymeric chain. The sterically-protected, N-methylated imidazolium polymers exhibit hydroxide stability in concentrated caustic solutions at elevated temperatures, such as at 100&#xb0; C. and higher.

Stable poly(imidazolium) hydroxides

Described herein are crosslinked alkylated poly(benzimidazole) and poly(imidazole) polymer materials and devices (e.g., fuel cells, water electrolyzers) including these polymer materials. The polymer materials can be prepared in a convenient manner, allowing for applications such as anion exchange membranes (AEMs). The membranes provide high anion conductivities over a wider range of operating conditions when compared to the analogous membranes that are not cross-linked. The crosslinked polymer materials have improved alkaline stability, when compared to the analogous non-crosslinked polymer materials.

Crosslinking of hydroxide stable, polybenzimidazoliums and polyimidazoliums membranes and ionomers

An agricultural sensing system includes multiple sensor and/or actuator modules configured to communicate with a relay unit. The sensor and/or actuator modules are powered using solar energy and contain no batteries. The modules feature sleep modes in which some circuits are placed in a low energy mode to conserve energy and remove the need for batteries. Communications to or from the relay unit are optionally timed to avoid interference between transmissions from different sensor and/or actuator modules. The relay units are configured to relay sensor data and send commands to the sensor and/or actuator modules.

Remote sensor system

An integrated circuit (IC) device can include at least one phase or delay lock loop (P/DLL) circuit comprising a plurality of circuit sections, at least one of the circuit sections responsive to digital calibration values to alter at least one periodic output signal; a nonvolatile memory (NVM) circuit formed in the same IC package as the at least one P/DLL circuit and configured to store the calibration values; and a processing circuit formed in the same IC package as the at least one P/DLL circuit and the NVM circuit, the processing circuit configured to generate the calibration values in response to target values and output values from the at least one P/DLL circuit, and to store the calibration values in the NVM circuit.

Integrated circuit device with on-board calibration of signal generator circuits, and related methods

A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.

Ternary content addressable memory (TCAM) cells with low signal line numbers

Built-in self-test (BIST) devices and methods are disclosed. A BIST section () according to one embodiment can include a built-in seed value memory () that stores multiple seed values. In a BIST operation, a seed value can be transferred from a built-in seed memory () to a test pattern generator () to generate multiple test patterns for scan chains (-to-). Successive seed values can be transferred to generate multiple test patterns sets at a clock speed and/or to achieve a desired test coverage.

Automatic built-in self-test of logic with seeding from on-chip memory

A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell () can include a pair of memory areas to store data (----), and a logic portion (--) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.

Interlocking memory/logic cell layout and method of manufacture

A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entries producing those false matches. While the entries producing a match should have the same index location, errors might cause those match lines to have an offset. If so, the present CAM, through use of duplicative sets of CAM locations, will detect the offset and thereafter the values in each index location that produces a match, along with the corresponding parity or error detection encoding bit(s). If the parity or error detection encoding bit(s) indicate an error in a particular entry, then that error is located and the corresponding entry at the same index within the other, duplicative set of CAM locations is copied into the that erroneous entry. Since duplicative copies are by design placed into the first and second sets of CAM locations, whatever value exists in the opposing entry can be written into the erroneous entry to correct errors in that search location. The first and second sets of CAM locations are configurable to be duplicative or distinct in content, allowing error detection and correction to be performed at multiple user-specified granularities. The error detection and correction during search is backward compatible to interim parity scrubbing and ECC scan, as well as use of FNH bits set by a user or provider.

Error correcting content addressable memory

A content addressable memory (CAM) device () can include a control block () having a dummy control circuit (). A dummy control circuit () can initiate dummy searches (or other operations) prior to and/or during actual searches to reduce overall supply current transients. Methods for initiating dummy searches are also disclosed.

Method and apparatus for smoothing current transients in a content addressable memory (CAM) device with dummy searches

A variable impedance output driver has been disclosed. One embodiment of the variable impedance output driver includes a first pull-up structure, a pull-down structure, and a comparator, coupled to the first pull-up structure and the pull-down structure, to calibrate the first pull-up structure and the pull-down structure against a reference impedance. Other embodiments are described and claimed.

Variable impedance output driver

A programmable serial interface device. The device generally comprises a programmable logic device and another die mounted to an assembly apparatus. The programmable logic device may comprise (i) a plurality of logic block clusters and (ii) a plurality of routing channels configured to interconnect said logic block clusters. The die may comprise a first communication channel (i) configured to convert between a first serial data signal and a first parallel data signal and (ii) coupled to a first of the routing channels to exchange the first parallel data signal with at least one of the logic block clusters.

Programmable serial interface

A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.

Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy

A method for interconnecting a plurality of dies. The method generally includes receiving a plurality of interconnect requirements for the dies. The interconnect requirements may include a priority for each of a plurality of nets. A position and an angle for one of the dies relative to a substrate may be calculated in response to the interconnect requirements. A plurality of nets may then be routed among the dies and a plurality of substrate pads defining external connections for the substrate. The dies may be mounted to the substrate after routing has been finalized.

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Mountain View, CA, United States of America

Andrew J Wright