General Dynamics Information Systems, Inc.

General Dynamics Advanced Information Systems, Inc.

Andrew J Wardrop

Stephen Fuchs

An apparatus and method for controlling the communication frequencies of a software controlled radio by using GPS to calibrate one or more local oscillators and compensating within the digital radio processing for the local oscillator inaccuracies. The apparatus and method receives and transmits radio frequency signals and includes an oscillator; a frequency monitor adapted to measure the frequency of the oscillator; a numerically controlled oscillator; and a computer adapted to receive the frequency measurement of the oscillator from the frequency monitor, to calculate an error associated with the oscillator, and to calculate a numerically controlled oscillator setting based on the calculation of the error associated with the oscillator; the numerically controlled oscillator adapted to receive the numerically controlled oscillator setting from the computer.

Apparatus and method for GPS-based digital compensation of radio frequencies

A method and apparatus for coordinating the activities of multiple computers using a common reference point such as a Global Positioning System pulse-per-second signal. A reload register transmits a reload value to a mission timer. The mission timer generates an interrupt signal based upon the reload value. A timer capture register captures the countdown value of the mission timer when a pulse-per-second signal is asserted. Software generates new reload values based upon the countdown value captured by the timer capture register. Additional timer capture registers may be used to form a consensus value of the countdown value when the pulse-per-second signal is asserted. A local pulse-per-second signal generator may be used when a Global Positioning System pulse-per-second signal is not available.

Apparatus and method for coordinating activities of one or more computers

An apparatus and method for controlling the communication frequencies of a software controlled radio by using GPS to calibrate one or more local oscillators and compensating within the digital radio processing for the local oscillator inaccuracies.

A computer system uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer includes four or more commercial processing units (CPUs) operating in strict 'lock-step' and whose outputs (33, 37) to system memory and system bus are voted by a gate array which may be implemented in a custom integrated circuit. A custom memory controller interfaces to the system memory and system bus. The data and address (35, 37) at each write to and read from memory within the computer are voted at each CPU clock cycle. A vote status and control circuit 'reads' the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals are used by the agreeing CPUs 32 to continue processing operations without interruption. The system logic selects the best chance of recovering from a detected fault by re-synchronizing all CPUs, powering down a faulty CPU or switching to a spare computer, resetting and re-booting the substituted CPUs.

Fault tolerant computer system

A non-intrusive power control for a fault tolerant computer system which uses redundant voting at the hardware clock level. The computer includes three or more commercial central processing units (CPUs) operating synchronously. Outputs to system memory and system bus are voted by a radiation tolerant gate array which may be implemented in a custom integrated circuit. An interface control coupled to the voter can remove or connect power from a CPU and adjust CPU inputs, preventing damage to the components without terminating an operating program. The inputs and outputs at each write to and read from system memory are voted at each CPU clock cycle. A vote status and control circuit 'reads' the status of the vote and controls the state of the CPUs using hardware and software. The system logic selects the best chance of recovering from a detected fault by re-synchronizing all CPUs, powering down a faulty CPU, or switching to a spare computer, resetting and re-booting the substituted CPU.

Non-interrupting power control for fault tolerant computer systems

A fault tolerant memory system having a triple bit error correction and quadruple bit error detection capability is disclosed using control logic coupled to multiple decoders each having single bit error correction/double bit error detection capabilities. The memory system can also be provided with a sparing system which provides an additional memory device to circumvent failures in individual memory devices. The memory system is suited for severe environments such as computing systems operating in outer space.

Fault tolerant memory system

A fault tolerant computer system is disclosed which uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer (30) includes four or more commercial processing units (CPUs) (32) operating in strict 'lock-step' and whose outputs (33, 37) to system memory (46) and system bus (12) are voted by a gate array (50) which may be implemented in a custom integrated circuit (34). A custom memory controller (18) interfaces to the system memory (46) and system bus (12). The data and address (35, 37) at each write to and read from memory (46) within the computer (30) are voted at each CPU clock cycle. A vote status and control circuit (38) 'reads' the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals (35) are used by the agreeing CPUs 32 to continue processing operations without interruption. The system logic selects the best chance of recovering from a detected fault by resynchronizing all CPUs (32), powering down a faulty CPU or switching to a spare computer (30), resetting and re-booting the substituted CPUs (32).

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Lakeville, MN, United States of America

Andrew J Wardrop