Cisco Technology, Inc.

Andrew J Thurston

Robert A Hall

Douglas E Duschatko

Lane Bryon Quibodeaux

Qiujie Dong

Lane Byron Quibodeaux

James Thomas Theodoras

Daniel Lee Chaplin

Various methods and systems for implementing Reed Solomon multiplication sections from exclusive-OR (XOR) logic are disclosed. For example, a system includes a Reed Solomon multiplication section, which includes XOR-based logic. The XOR-based logic includes an input, an output, and one or more XOR gates. A symbol X is received at the input of the XOR-based logic. The one or more XOR gates are coupled to generate a product of a power of &#x3b1; and X at the output, wherein &#x3b1; is a root of a primitive polynomial of a Reed Solomon code. Such a Reed Solomon multiplication section, which can include one or more multipliers implemented using XOR-based logic, can be included in a Reed Solomon encoder or decoder.

System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic

An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. If the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

BCH forward error correction decoder

A method, apparatus and system are disclosed that more efficiently maps data into standard SONET concatenated payloads for transmission over established SONET networks. Framing information is added to a data stream to identify the beginning and ending locations of a payload. Next, the framed data stream is formatted into a non-standard STS-Nc packet. Two or more non-standard STS-Nc packets are combined to form a pseudo-standard STS-Nc packet that is supported by the established SONET network. According to one embodiment, a one Gbps Ethernet packet is framed using HDLC formatting, then formatted into an STS-24packet. Two STS-24packets are combined to form a pseudo-standard STS-48packet. In addition, the one Gbps Ethernet packet can be stored and retimed to the SONET data rate and transmitted across an established SONET network.

Non-standard concatenation mapping for payloads

An apparatus and method of implementing a circuit representing a complex polynomial equation in a hardware description language (HDL) for implementing an ASIC (Application Specific Integrated Circuit) is provided. A serial circuit representing the complex polynomial equation is implemented in a software program. The serial circuit implementation is simulated to produce a plurality of parallel equations that are mapped into HDL with ASCII strings. In one embodiment, the complex polynomial equation is a Bose-Chaudhuri-Hocquenghem (BCH) code utilized in forward error correction circuitry.

Automatic generation of hardware description language code for complex polynomial functions

An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. In the specific embodiment wherein the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

Galois field multiply accumulator

An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. An error insertion circuit is also provided for verifying correct operation of encoding and decoding circuits. A desired number of errors may be programmed for insertion into the OC-48 data signals. Error insertion may be performed in an iterative fashion to insert into different data signals the desired number of errors, wherein the errors are placed within the code words of the data signals at different location permutations for each data signal. In one implementation, error verification is performed using an error accumulator located in the receiver, and means are provided for examining an error accumulator count of the error accumulator to see if the number of accumulated errors matches with the number of inserted errors.

Error insertion circuit for SONET forward error correction

In a data transmission network, such as SONET, a method and apparatus for the generation of a path Alarm Insertion Signal (AIS) at the output of each of a number of concatenated pointer processors in response to a failure at the input of any one of the pointer processors. Each of the pointer processors has an input, an output and a bidirectional terminal that is coupled to a common node. Each of the pointer processors includes circuitry coupled to the input, the output and the bidirectional terminal that causes a predetermined logic level to be asserted at the bidirectional terminal in response to the appearance of an error signal at its input and that causes an AIS to appear at its output in response to either an error signal at its input or the assertion of the predetermined logic level at its bidirectional terminal.

Path AIS insertion for concatenated payloads across multiple processors

A method of generating a parity value is disclosed. The method includes reading a word from a data stream, determining if the word should be included in a parity calculation, and including the word in the parity calculation, if the word should be included in the parity calculation, and ignoring the word otherwise.

Method and apparatus for detecting errors in a backplane frame

An apparatus and method for a synchronous optical network (SONET) includes ordering a plurality of signals of a first type in one or more line cards for transmit to one or more types of line cards, wherein the ordering of the first type of signals creates a plurality of independent signals of a second type, and transmitting the plurality of the first type of signals to the one or more types of line cards, wherein the independence of the signals of the second type permits the one or more types of signals of the second type to be in an arbitrary order. The method and apparatus includes ordering in a plurality of modules to assign to a variable A a number of basic modules on the one or more line cards, assign to a variable B a number of processors adapted for STS-N signals on the one or more line cards, calculate a variable C by dividing A by B, C being the number of basic module channels common to each of the processors, calculate a variable D by dividing C by three, D being a number of contiguous channels, divide each STS-N signal into N/D portions, each portion including up to D bytes, and for each portion of the STS-N signal, select one of the number of processors adapted for STS-N signals, and transmit the portion of the STS-N signal to the one of the number of processors.

Channel ordering for communication signals split for matrix switching

A method for high-speed signal framing of an incoming bit stream includes receiving the incoming bit stream in a datapath and locating a predetermined framing pattern in the datapath by finding a predetermined number of repetitions of a first portion of the framing pattern, bit aligning the bits in the datapath based on the predetermined number of repetitions of the first portion, priority encoding bits in a next cycle of the datapath, identifying a location of a second portion of the framing pattern, word aligning the priority encoded bits. The method includes declaring the bit stream as in frame. The incoming bit stream is over a datapath of at least 64 bits and the predetermined number of repetitions is at least three repetitions. Further, the incoming bitstream is a parallelized bitstream, the parallelization being performed in a shift register. An apparatus disposed in a communication system includes a shift register to receive an incoming bitstream that is configured to parallelize the incoming bitstream, a bit-aligning multiplexer coupled to the shift register that bit-aligns the parallelized bitstream according to a first portion of a framing pattern, a priority encoder coupled to the bit-aligning multiplexer that locates a priority byte in the parallelized bitstream identified in a second portion of the framing pattern and identifies a transition between the first portion and the second portion of the framing pattern, a byte-aligning multiplexer coupled to the priority encoder that byte-aligns the parallelized bitstream according to the priority byte and determining frame borders of the incoming bitstream.

Method and apparatus of framing high-speed signals

An apparatus and method for detecting concatenation of payload data for an communication circuit is disclosed, wherein the payload data is dispersed over a first integrated circuit and one or more subsequent integrated circuits. The method and apparatus include determining whether each of the one or more subsequent integrated circuits have all channels therein designated as concatenation slaves, and communicating the determination to the first integrated circuit, the determination indicating that the one or more subsequent integrated circuits. According to an embodiment, the method and apparatus further include coupling the first integrated circuits to the one or more subsequent integrated circuits. The apparatus and method further include detecting concatenation on a first integrated circuit of the one or more integrated circuits, assigning one or more bi-directional ports coupled to the first integrated circuit as an input port, assigning each bi-directional port coupled to the one or more subsequent integrated circuits as output ports, and if any one integrated circuit among the subsequent integrated circuits includes a channel therein designated as a slave channel, providing an active high signal to the output port, the active high signal coupled to the input port of the first integrated circuit.

Concatenation detection across multiple chips

A method for testing a signal path for mark ratio tolerance includes generating a varying test pattern by selecting between a first pattern and a second pattern according to a defined sequence; and sending the varying test pattern over the signal path. An apparatus disposed in a communication system includes a selection circuit for generating a varying test pattern to send over the signal path, the selection circuit generating the varying test pattern by selecting between a first pattern and a second pattern according to a select sequence signal, and a sequencer coupled to the selection circuit, the sequencer providing the select sequence signal to the selection circuit, the sequencer generating the select sequence signal according to a mode value. The mark ratio tolerance of a system can be tested, varying the data density of one portion of the signal path while maintaining a constant data density on another portion of the signal path.

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Allen, TX, United States of America

Andrew J Thurston