Nvidia Corporation

Andrew J Tao

Henry Packard Moreton

Vimal S Parikh

Jerome Francis Duluk, Jr

Bryan Catanzaro

Shiqiu Liu

Yan Yan Tang

Robert Pottorff

Rui Manuel Bastos

Lordson L Yue

Matthieu Le

Jesse David Hall

Ting-Chun Wang

Johnny S Rhoades

David Tarjan

Kevin Shih

John Douglas Tynefield, Jr

Karan Sapra

Guilin Liu

Fitsum A Reda

John Stephen Montrym

Emmett Michael Kilgariff

James Leroy Deming

Jeffrey A Bolz

Cass Watson Everitt

Yury Y Uralsky

Patrick Richard Brown

Alexander Lev Minkin

Bryon S Nordquist

Eric T Anderson

Roger L Allen

Christian Amsinck

Jonathan J Dunaisky

Dominic Acocella

Svetoslav D Tzvetkov

Zhiding Yu

Poornachandra Rao

Animesh Garg

Elena Ing

Mark R Goudy

Amanpreet Grewal

John A Robinson

Makarand M Dharmapurikar

Aysegul Dundar

Jarmo Lunden

Brandon Rowlett

A neural network architecture is disclosed for performing image in-painting using partial convolution operations. The neural network processes an image and a corresponding mask that identifies holes in the image utilizing partial convolution operations, where the mask is used by the partial convolution operation to zero out coefficients of the convolution kernel corresponding to invalid pixel data for the holes. The mask is updated after each partial convolution operation is performed in an encoder section of the neural network. In one embodiment, the neural network is implemented using an encoder-decoder framework with skip links to forward representations of the features at different sections of the encoder to corresponding sections of the decoder.

Image in-painting for irregular holes using partial convolutions

Apparatuses, systems, and techniques are presented to generate images with one or more visual effects applied. In at least one embodiment, one or more visual effects are applied to one or more images having a resolution that is less than a first resolution and those visual effects approximated for one or more images having a resolution that is greater than or equal to the first resolution.

Image enhancement using one or more neural networks

Apparatuses, systems, and techniques are presented to generate one or more images. In at least one embodiment, two or more pixels from two or more images are blended based, at least in part, on a distance of the two or more pixels from a region of the two or more images, in which pixel colors are substantially similar.

Pixel blending for neural network-based image generation

Apparatuses, systems, and techniques for texture synthesis from small input textures in images using convolutional neural networks. In at least one embodiment, one or more convolutional layers are used in conjunction with one or more transposed convolution operations to generate a large textured output image from a small input textured image while preserving global features and texture, according to various novel techniques described herein.

Techniques to use a neural network to expand an image

Apparatuses, systems, and techniques to enhance video are disclosed. In at least one embodiment, one or more neural networks are used to create a higher resolution video using upsampled frames from a lower resolution video.

Video upsampling using one or more neural networks

Apparatuses, systems, and techniques to enhance video are disclosed. In at least one embodiment, one or more neural networks are used to create, from a first video, a second video having one or more additional video frames.

Video prediction using one or more neural networks

One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.

Managing memory regions to support sparse mappings

A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.

Determining a working set of texture maps

Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.

Sparse texture systems and methods

An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a storage unit and a reorder control unit that is connected to the storage unit. The reorder control unit is configured to coordinate storage of vertex attributes in the storage unit so as to convert the vertex attributes from an initial order to a modified order. The reorder control unit is configured to identify a subset of the vertex attributes to be stored within a common range of addresses in the storage unit, and the reorder control unit is configured to access the storage unit such that the subset of the vertex attributes is written into the storage unit substantially in parallel.

Buffering unit to support graphics processing operations

Growing community of inventors

San Francisco, CA, United States of America

Andrew J Tao