Texas Instruments Corporation

Surecore Limited

Andrew J Pickering

Simon D Forey

Peter Hunt

Susan M Simpson

Bhajan Singh

Tom Leslie

Robert Simpson

Giuseppe Surace

Andrew D Stewart

Andrew Keith Joy

Richard Ward

Benjamin James Kerr

Shaun Lytollis

Sue Simpson

There is provided a memory unit (). The memory unit comprises a plurality of memory cells (), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (), a pre-charge circuit () configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplayer circuit () comprises, for each bit line, an associated NMOS () device that is configured to selectively connect the bit line () to the data input and output circuitry and to the pre-charge circuit () when activated by a corresponding bit line selection signal, and a multiplex controller () that is configured to be able to select each pair of bit lines by activating the associated NMOS devices () using the corresponding bit lines selection signals.

Memory unit

There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.

SRAM cells

The present invention provides a memory unit () comprising: a storage element () comprising a pair of back to back inverters (and) having respective first and second storage access nodes (); first and second voltage lines (VSS, VDD) across which said pair of back to back inverters (and) are connected; a first access transistor (), connected to said first storage node (); a second access transistor (), connected to said second storage node (); a write word line () connected to a gate () on said first access transistor () and a gate () on said second access transistor (); a first bit line () operably connected for controllingsaid node (); a second bit line () operably connected for controlling said node (); in which there is provided a data dependent conductive path () between the first and second bit lines ().

Low-power SRAM cells

The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90&#xb0;. This feature is useful in clock/data recovery where the 90&#xb0; 'jumps' can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.

Phase interpolator with independent quadrant rotation

A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each of a subset of the modes of the multi-mode circuit a corresponding debug signal based on a clock signal provided at the input. The frequency of debug signals is dependent on the frequency of a clock signal provided at the input, and each debug signal selects its respective mode for a length of time longer than that of each other mode of the multi-mode circuit, or each debug signal selects its respective mode for a length of time shorter than that of each other mode of the multi-mode circuit.

Debug circuit and a method of debugging

The present invention relates to controlling the timing of a clock signal in high speed circuits, such as an analogue-digital converter (ADC). In some high speed data transfer techniques, the incoming data is latched using a clock signal. Often, the delay between the incoming data being clocked into the circuit and being ready to use (referred to as the 'clock-to-Q period') is large enough to cause problems. In particular, the clock-to-Q period may be sufficient to result in the original clock signal being inappropriate to clock the latched signal. The present invention provides a data capture circuit with matched latch to address this issue, particularly a first latch having an input for receiving a data input signal; a first sense amplifier having an input coupled to an output of the first latch; a second latch having an input coupled to the output of the first sense amplifier and an output providing a first data output; and a clock generator, the clock generator comprising: a third latch having an input for receiving a first clock signal; a second sense amplifier having an input coupled to an output of said third latch; and a fourth latch having an input coupled to an output of said second sense amplifier and an output providing a first adjusted clock signal, wherein said first and third latches are substantially the same, the first and second sense amplifier are substantially the same and the second and fourth latches are substantially the same.

Clock generator

Clock recovery apparatus having an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein the early/late voter passes and Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplierfor generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and the interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that the sampling point can be advanced or retarded.

Clock recovery

A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably the negative impedance cell has a pair of back to back transistors, and connected thereto a parallel resistor capacitor RC network. The basic equalizer stage has a pair of current sources; a pair of transistors arranged as a differential pair, each transistor connected to a different one of the current sources; and a degeneration impedance connected in between the two current sources, and the transistors, wherein the negative impedance cell is connected across the outputs of the pair of transistors.

High bandwidth high gain receiver equalizer

There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs, and each load comprises an integrator.

Triangulating phase interpolator

There is provided a method and apparatus for performing an eye scan. Said apparatus comprises: a receiver for receiving input signals; an equaliser for processing said input signals; a data sampler for sampling said processed input signals at certain sampling points to produce a data output, said data sampler being controlled by a clock signal; an edge sampler for detecting the edges of the processed input signal; an early/late voter for deciding whether a current sampling point needs to be advanced or retarded. The early/late voter passes an Up/Down signal to an interpolator for maintaining said clock signal, said interpolator acting on said Up/Down signal to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.

Apparatus and method for performing eye scan

A steering current generator for a phase interpolator has a multiplicity of fine phase adjustment current sources, each of which is switchable to direct its current to one or other of two summing nodes. The current of each of those two summing nodes is supplemented by respective fixed always-on current sources. The steering current generator has four current outputs and a switching matrix is provided to switch the current from the summing nodes to first and second selected ones of those outputs. The switching matrix is also connected to switch bleed currents to the other two of the current outputs.

Interpolation

There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.

Duty cycle controlled CML-CMOS converter

A digital system aligns a set of serial data receiver demultiplex circuits, thereby aligning the bits in the data words, while maintaining separate and optimally aligned data recovery clocks for each channel. The digital system generates a reference clock signal and one or more slave clock signals. Phase circuitry receives the slave clock signal and outputs a plurality of clock phase signals. A phase selection circuit receives the plurality of clock phase signals and selects an adjusted clock signal in response to a phase selection signal. A clock correlation circuit determines a phase difference between the reference clock signal and the adjusted clock signal and provides the phase selection signal to minimize the phase difference. The clock correlation circuit provides the phase selection signal from a counter.

High speed parallel link receiver

A differential data transmission system that transmits encoded data symbols as differential signals. A signal for transmitting symbols on a set of at least three parallel channels, each channel having a first terminal, Pto PN, and each channel having a second terminal connected to a common node Z. The signal comprising for each symbol an active signal on two of those channels and an inactive signal on the remaining channel or channels, the symbols being distinguishable by which two of the channels have the active signals.

Systems for data transmission

Apparatus for generating an oscillating signal in a desired phase relationship with an input signal, including a mixer arranged to receive a pair of reference signals oscillating at a common frequency and having a phase offset between them, and to mix the reference signals in variable proportions according to the value of input weighting signals to generate an output signal. A comparator is to compare the phase of the output signal with that of the input signal to determine whether the signals are in the desired phase relationship and, if not, to output one or more control signals indicative of the required adjustment in the phase of the output signal to achieve the desired phase relationship. An adjustable ring oscillator including a plurality of stages is connected in a ring and arranged to propagate oscillations around the ring. The ring oscillator is responsive to one or more control signals to propagate the oscillations in first and second directions around the ring and is arranged to provide the weighting signals to the mixer from outputs of ones of its stages.

Growing community of inventors

Warks, United Kingdom

Andrew J Pickering