Linear Technology Corporation

Analog Devices International Unlimited Company

Analog Devices,inc.

Andrew J Gardner

David McLean Dwelley

Heath Stewart

Jeffrey Lynn Heath

Gitesh Bhagwat

Robert Chiacchia

Gregory Jon Manlove

Michael B Anderson

Matthew Joseph Maloney

David Stover

Yiding (Eric) Gu

Hellmuth Stephen Witte

Greg Jon Manlove

Srikanth Govindarajulu

Michael T Paul

A network node device for coupling to a network via a shared link that carries power and data. The network node device includes: one or more data transceivers to transmit and receive data over the shared link; physical layer circuitry (PHY) to transmit and receive data with the one or more data transceivers; and a galvanic isolation barrier coupled between the PHY and the one or more data transceivers, wherein the PHY transmits and receives the data with the one or more data transceivers over the galvanic isolation barrier.

Isolated transceiver for power over ethernet

A PoDL system that uses a center-tapped transformer, for galvanic isolation of the PHY, has AC-coupling capacitors in series between the transmission wires and the transformer's secondary windings for blocking DC voltages generated by a PSE power supply. The center tap is conventionally connected to ground. As a result, one capacitor sees the full VPSE voltage across it, and the other capacitor sees approximately 0 V across it. Since the effective value of a ceramic capacitor significantly reduces with increasing DC bias voltages across it, the effective values of the capacitors will be very different, resulting in unbalanced data paths. This can lead to conversion of common mode noise and corrupt the data. To avoid this, a resistor divider is used to generate VPSE/2, and this voltage is applied to the center tap of the transformer. Therefore, the DC voltage across each capacitor is approximately VPSE/2, so their values remain equal.

Minimizing DC bias voltage difference across AC-blocking capacitors in PoDL system

A Power over Data Lines (PoDL) system provides a DC voltage and differential data signals on the same wire pair. A Powered Device (PD) load is coupled to the wire pair, via a gyrator, for being powered by the DC voltage. The gyrator emulates the DC-coupling properties of inductors using active components. The gyrator includes transistors that are controlled to act as a full-bridge rectifier for ensuring a correct polarity DC voltage is applied to the PD load. Since the transistors operate in saturation and are coupled to be insensitive to differential data signals on the wire pair, the current supplied to the PD load is substantially unaffected by the differential data signals. Negative feedback circuits in the gyrator reduce fluctuations in current through the gyrator due to differential data signals on the wire pair. No inductors are required in the gyrator. A PHY is AC-coupled to the wire pair via capacitors.

PoDL powered device with active rectifier bridge to obviate the need for DC-coupling inductors

A Power over Data Lines (PoDL) system includes a Powered Device (PD) logic circuit for conveying classification information to Power Sourcing Equipment (PSE), during a classification phase, via a wire pair. The logic circuit controls a shunting switch for selectively shunting the wires together for communication with the PSE during the classification phase. A holdup capacitor supplies power to the logic circuit during the classification phase. The logic circuit controls a full-bridge rectifier to ensure the capacitor is charged with a proper polarity voltage and to ensure a proper polarity voltage is supplied to a PD load. The PD has a controller for controlling the rectifier to cause a current path between terminals of the capacitor, via the shunting switch, when the shunting switch is to be turned on.

PoDL powered device with active rectifier bridge and shunting switch

In a Power over Data Lines (PoDL) system that conducts differential data and DC power over the same wire pair, various DC coupling techniques are described that improve DC voltage coupling while attenuating AC common mode noise and avoiding mode conversion. A first CMC and AC coupling capacitors are connected in series between a PHY and a twisted wire pair. A DC power supply is DC coupled to the wires via a series connection of a DMC and either matched inductors or a second CMC. Coupled between the DMC and the inductors/CMC is an RC termination circuit comprising a first capacitor coupled to one leg and a matched second capacitor coupled to the other leg. The two capacitors are connected to the same resistor coupled to ground.

Power over data lines system with combined dc coupling and common mode termination circuitry

A PoDL system uses a gyrator for DC coupling of DC power from a PSE to a wire pair, and/or decoupling DC power from a wire pair for a PD. The gyrators obviate the use of discrete inductors for DC-coupling/decoupling and can be formed as an integrated circuit. The gyrators use a small integrated capacitor and invert and multiply the capacitor effect to emulate an inductor. The gyrators present a high impedance to AC current and a low impedance to DC current. Various gyrator designs, such as positive and negative polarity gyrators, and configurations are disclosed. Gyrators are described with analog current limit and power switch control, so multiple functions are integrated on the same IC chip.

Active gyrator circuit in one-pair ethernet with PoDL

A PoE system includes a PSE connected via a shielded twisted wire pair to a PD, where differential data is transmitted over only the wire pair, and where DC power is transmitted via the wires in the wire pair conducting a DC voltage in parallel while using the shield conductor as ground. A low power handshaking routine is performed by a PSE controller and a PD controller by conducting a source current through the wires in parallel and a return current through the shield conductor. Center tap auto-transformers are used to connect the two wires to the PSE and PD controllers and to a DC voltage source in the PSE. After a successful handshaking routine, the PSE couples the DC voltage source between the wire pair and the shield conductor by closing a first power switch. The PD controller then closes a second power switch to power a load.

Power over ethernet using shielded single twisted wire pair

In an Intrinsically Safe (IS) PoDL/PoE system, a PHY in power sourcing equipment (PSE) has its differential transmit terminals coupled across a primary winding of an isolation transformer. One secondary winding is coupled between a positive terminal of a DC voltage source and a first wire of a twisted wire pair. Another secondary winding is coupled between a negative terminal (e.g., ground) of the DC voltage source and a second wire of the twisted wire pair. The secondary windings provide differential data signals output from the PHY's transceiver to the wire pair, while the DC voltage from the DC voltage source is coupled to the wire pair via the two secondary windings. The DC power is applied to a remote power device having a PHY that communicates with the PSE PHY. Therefore, the secondary windings have the dual purpose of DC-coupling and magnetically coupling the differential data to/from the PHY.

Galvanic barrier coupler for intrinsically safe power over data line applications

One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.

Fault-tolerant power network

In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuity to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

Communications system using hybrid common mode choke and kelvin sensing of voltage

Various techniques are described to terminate a differential wire pair using combinations of CMCs, transformers, autotransformers, differential mode chokes (DMCs), and AC-coupling capacitors. The techniques improve the AC common mode insertion loss without attenuating the differential data signals, while easing the requirements of the CMC. In one example, an autotransformer, having a first winding, a second winding, and a center tap, is connected across a PHY, where the center tap provides a low impedance to ground for attenuating common mode noise. A CMC is coupled across the autotransformer and a pair of wires carrying differential data, where the CMC greatly attenuates common mode noise. The requirements of the CMC are reduced due to the autotransformer.

Common mode noise attenuation techniques for twisted wire pair

In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuitry to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

In one embodiment, a master device has a first port and a second port and initially applies a DC voltage only to the first port. A plurality of slave devices, each have a third port and a fourth port, are serially connected to the master device in a ring, via conductors, starting at the first port and ending at the second port. The conductors simultaneously carry the DC voltage and differential data. Each slave device, after performing a detection routine, then sequentially applies the DC voltage to the adjacent downstream slave device in a first direction around the ring. If the master does not detect the presence of the DC voltage at its second port, the master device applies the DC voltage to both the first port and the second port to sequentially power up the slave devices in both directions around the ring of slave devices.

Power over data lines system with redundant power connections

In one embodiment, a PoDL system includes a PSE that uses high side and low side circuit breakers that uncouple the PSE voltage source from the wire pair in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires. The breakers perform an automatic retry operation in the event the fault has been removed. The voltages on the wires in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed.

Circuit architectures for protecting against PoDL wire faults

Circuits and techniques are described for detecting a ground fault leak between the PSE and the PD. Prior to PoDL voltage being applied to the PD, a test switch is temporarily closed for sensing a voltage drop in a loop between the positive terminal of the PSE voltage source and any ground leakage path between the PSE and the PD. If the resistance of the ground leakage path is below a certain threshold, a fault is declared. A similar test may be performed without a test switch by supplying a known test current through the loop and sensing the voltage drop. Another test is to connect the positive terminal of the PSE voltage source to the loop and sense the resulting current. After the full PoDL voltage is applied to the PD, a ground fault may be detected by sensing the equivalence between the source and return PSE currents.

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Santa Barbara, CA, United States of America

Andrew J Gardner