Xilinx, Inc.

Andrew J DeBaets

Robert W Wells

Robert D Patrie

According to an embodiment, an die for routing signals in a plurality of metal layers of an integrated circuit device is disclosed. The die comprises a first pair of conductive lines (A andB) having a first reference line and a first signal line, the first reference line having traces and crossover segments in a plurality of metal layers; and second pair of conductive lines (A andB) having a second reference line and a second signal line, the second reference line having traces and crossover segments in the plurality of metal layers which are offset from the traces and crossover segments of the first reference lines; wherein a first signal trace () of the first signal line in a first metal layer is adjacent to a first reference trace () of the first reference line on a first side of the first signal trace and to a second reference trace () of the second reference line on a second side of the first signal trace. A method for routing signals in a plurality of metal layers of an integrated circuit device is also disclosed.

Circuit for and method of routing signals in a plurality of metal layers of an integrated circuit

An integrated circuit with capacitor structures includes a substrate and a plurality of vias extending from a front surface to a back surface of the substrate. A plurality of transistors is disposed at the front surface of the substrate and has first and second pluralities of electrodes. A patterned metal layer on the front surface of the semiconductor substrate provides first and second networks. The first network couples the first plurality of electrodes to a first via, and the second network couples the second plurality of electrodes to a second via. A dielectric layer separates first and second patterned metal layers on the back surface of the substrate. The first patterned metal layer includes a first metal plate coupled to the first via, and the second patterned metal layer includes a second metal plate coupled to the second via, forming a capacitor with the dielectric layer.

Integrated circuit having capacitor on back surface

Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.

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Cupertino, CA, United States of America

Andrew J DeBaets