Texas Instruments Corporation

Wolfson Microelectronics Limited

Andrew J Cringean

Eric G Soenen

Kirk D Peterson

James E Nave

James R Craig

An analogue to digital converter (ADC) of the recirculating type is described. In one embodiment, the ADC is composed of three storage and residual determination units, which, in cooperation with an operational amplifier, and suitable comparator means, are operable to re-present residual signals for analogue to digital conversion. To enhance settling at the beginning of a cycle, the first storage and residual determination unit is used once, with remaining recirculation being conducted between the other two storage and residual determination units. Another embodiment presents a recirculating ADC stage which comprises a plurality of capacitor banks operable to be switched into and out of connection with other components of the ADC stage, in order to recirculate residual values for calculation of further bits of a digital output. Each bank comprises a plurality of capacitors, and cooperating switching means for connecting each bank in turn with the other components. The switching means are controlled by timing signals, wherein the switching means for each capacitor in each capacitor bank interpose the same number of switches between that capacitor and fed-back signals to that capacitor as to other capacitors of that bank.

Analogue to digital converter

An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) in the analog domain. A triple sample/hold circuit 2a samples the RGB signals simultaneously, multiplexes the data and passes the three signals on the ADC 2b sequentially (at about 3 times the data rate). The sample/hold circuit 2a has the capability to operate in fully differential as well as single ended input mode, and can perform correlated double sampling if needed. A high resolution ADC 2b converts the 3 multiplexed signals from simple/hold circuit 2a. A first digital offset correction circuit 2f restores the level of the RGB signals in the digital domain on a pixel by pixel basis. A first digital gain correction circuit 2g compensates for sensitivity variations of the RGB sensors in the digital domain on a pixel by pixel basis. A second digital offset correction circuit 2h restores the overall DC level of the RGB signals in the digital domain. A second digital gain correction circuit 2i compensates for overall sensitivity variations of the RGB sensors in the digital domain. A serial interface 2d is used to load the overall gain and offset coefficients.

Growing community of inventors

Edinburgh, United Kingdom

Andrew J Cringean