Apple Inc.

Andrew J Copperhall

Bo Yang

Bibo Li

Derek Keith Shaeffer

Henry C Jen

Xiang Lu

Vijay M Bettada

Karthik Manickam

Sagar Nataraj

Shriram Vijayakumar

Design-for-test (DFT) architectures, and methods of testing an array of chips, which may be identical, are described. In an embodiment, a comparison circuit includes a plurality of comparators to compare scan-data out (SDO) data streams with an expected data stream and transmit a compared data stream that is indicated of whether or not an error exists in any of the SDO data streams.

Test-response comparison circuit and scan data transfer scheme in a DFT architecture for micro LED based display panels

A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.

Hardware assisted scheme for testing memories using scan

Techniques are disclosed relating to test equipment. In one embodiment, a method includes receiving failure information from a first test of a device under test (DUT). In this embodiment, the DUT includes a plurality of scan chains that each include a plurality of scan cells. In this embodiment, the first test is based on a first compressed test pattern. In this embodiment, the failure information does not permit a definitive determination as to which scan cell is a failing scan cell. In this embodiment, the method includes generating a plurality of compressed test patterns based on the first compressed test pattern. In this embodiment, the plurality of compressed test patterns specify one-to-one-modes. In this embodiment, the method includes performing one or more second tests of the DUT using the plurality of compressed test patterns to definitively determine one or more failing scan cells.

Compressed scan testing techniques

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Redwood City, CA, United States of America

Andrew J Copperhall