Volterra Semiconductor Corporation

Inphi Corporation

Maxim Integrated Products, Inc.

Telegent Systems, Inc.

Andrew J Burstein

Anthony J Stratakos

David B Lidsky

Michael D McJimsey

Ilija Jergovic

Andrea Pizzutelli

Giovanni Garcea

William Albert Clark

Aaron M Schultz

David T Wang

Sombuddha Chakraborty

Jeremy M Flasck

Yali Xiong

Alexandr Ikriannikov

Charlie Sullivan

Marco A Zuniga

Budong You

Trey Roessig

Charles Nickel

Luigi Panseri

Biljana Beronja

Phong T Nguyen

Paul H Choi

Theodore Vinko Burmas

Lawrence Tse

Nirmal Raj Saxena

Carl W Pobanz

Brett A Miwa

Shaori Guo

Serhii Mikhailovich Zhak

Salvatore Giovanni Pastorina

Xin Zhou

Justin Michael Burkhart

Michael Warren Baker

Chien-Hsin Lee

Tonio Gaetano Biondi

Thurein Soe Paing

Michael Christenson

Jizheng Qiu

Javier Villagomez

Zabih Toosky

Zu Bing Yuan

Larry Kan

Srinivas Bamdhamravuri

Paul Murtagh

A method for controlling a switched tank converter (STC) includes (a) driving a first resonant tank circuit of the STC at a first frequency and with a first fixed on-time, to obtain a first fixed ratio of output voltage of the STC to input voltage of the STC, while the STC is powering a load having a first magnitude and (b) driving the first resonant tank circuit of the STC at a second frequency and with the first fixed on-time, to obtain the first fixed ratio of output voltage of the STC to input voltage of the STC while the STC is powering a load having a second magnitude. The second frequency is smaller than the first frequency, and the second magnitude is smaller than the first magnitude.

Variable switching frequency switched tank converters and associated methods

A method for controlling a number of phases that are active in a multiphase direct-current-to-direct-current (DC-to-DC) converter includes (a) filtering a current signal representing a magnitude of current processed by the multiphase DC-to-DC converter to generate a filtered signal, (b) comparing the filtered signal to a first threshold value, (c) deactivating one or more phases of the multiphase DC-to-DC converter in response to the filtered signal falling below the first threshold value, (d) comparing the current signal to a second threshold value, the second threshold value being greater than the first threshold value, and (e) activating one or more phases of the multiphase DC-to-DC converter in response to the current signal rising above the second threshold value.

Systems and methods for DC-to-DC converter control

An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is, for example, included in an integrated electronic assembly.

Integrated circuits including magnetic devices

A regulated, power supply system is described using multiphase DC-DC converters with dynamic fast-turnon, slow-turnoff phase shedding, early phase turn-on, and both load-voltage and drive-transistor feedback to pulsewidth modulators to provide fast response to load transients. In an embodiment, a system master can automatically determine whether all, or only some, slave phase units are fully populated. The programmable system includes fault detection with current and voltage sensing, telemetry capability, and automatic shutdown capability. In an embodiment, these are buck-type converters with or without coupled inductors, however some of the embodiments illustrated include boost configurations.

A coupled inductor array has length, width, and height. The coupled inductor array includes a monolithic magnetic core formed of a magnetic material having a distributed gap, and a plurality of windings embedded in the monolithic magnetic core. Each winding forms a respective winding loop of one or more turns around a respective winding axis, and each winding axis extends in the height direction. Areas of the monolithic magnetic core enclosed by the winding loops are greater than areas of the monolithic magnetic core outside of the winding loops, as seen when the coupled inductor array is viewed cross-sectionally in the height direction. One possible application of the coupled inductor array is in a multi-phase switching power converter.

Coupled inductor arrays and associated methods

An interface device for a memory module comprising a plurality of DRAMs includes a memory configured to store DRAM test program instructions, and a programmable processing device coupled to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions.

Memory test sequencer

A method for manufacturing a dynamic random access memory device is provided. The method includes fabricating a dynamic random access memory device having a plurality of memory cells. Each of the memory cells has a refresh characteristic that meets or exceeds a refresh specification provided for a DDR3 SDRAM device or a DDR4 SDRAM device. The method includes testing the dynamic random access memory device. The testing includes determining the refresh characteristic for each of the memory cells, classifying each of the memory cells as a good memory cell or a bad memory cell based upon the refresh characteristic, identifying each of the bad memory cells, and storing an address location for each of the bad memory cells. The method then includes transferring the address location for each of the bad memory cells into an address match table.

Memory parametric improvements

An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die. The second metallic lead forms a second winding turn around a portion of the magnetic core. The first and second winding turns are offset from each other along both of the width and length of the magnetic core. The integrated circuit is included in an integrated electronic assembly.

An integrated circuit memory interface device coupled to a dynamic random access memory device is provided. The device includes an address match table. The address match table includes a plurality of first addresses. Each of the first addresses is associated with a memory cell having a refresh characteristic outside of a specification for a DRAM device. The device has a plurality of second addresses. Each of the second addresses is associated with a refresh characteristic within a specification of the DRAM device and outside of a predetermined refresh characteristic range characterized to eliminate accesses to memory cells not meeting the predetermined refresh characteristic range.

The present system and method manage a rechargeable battery comprising two or more battery cells or series stacks of cells. The system includes a set of switches, each of which connects a cell or stack of cells between positive and negative nodes when actuated, or connects one cell in a stack of cells to another cell in the stack when actuated, such that when all the switches in a given stack are actuated, it is connected between the positive and negative nodes. An electrical load is directly connected to the positive and negative nodes. A controller determines the state of each cell or stack of cells by measuring and/or calculating one or more predetermined characteristics, and selectively actuates the switches based on the states of the cells or stacks of cells so as to enhance the life of the battery.

System and method for managing parallel-connected battery cells

A clock driver integrated circuit device and method is provided. The device can include a VTT regulator provided on a single integrated circuit (IC) chip. A first termination at an internal VDD/2 can be coupled to the VTT regulator. A VTT bus can be coupled to the first termination. A plurality of command control inputs can be coupled to the VTT bus. The plurality of command inputs can include A, BA, RAS, CAS, WE, CS, CKE, ODT, PARIN, and the like. A VDD termination can be coupled to a first end of the VTT bus and a ground can be coupled to a second end of the VTT bus. The method can include regulating or removing signal noise from a host controller via the clock driver IC device.

High speed digital signal termination circuit

Boot-up delay within a television receiver IC is substantially reduced by loading a portion of an operating program into the television receiver IC to enable execution of time-consuming receiver initialization operations, and then executing the receiver initialization operations concurrently with loading the remainder of the operating program into the television receiver IC. By this operation, the time required to execute the receiver initialization operations may be at least partly hidden under the time required to load the operating program, thereby substantially reducing the boot-up delay.

Fast-booting broadcast television receiver

Growing community of inventors

Pleasanton, CA, United States of America

Andrew J Burstein