Broadcom Corporation

Andrew Hwang

Thanh Tran

Steven B Lindsay

Andrew M Naylor

Henry Chou

Wei W Wang

Scott C Denton

Michael Asker

Scott Sterling McDaniel

Jonathan Fuchuen Lee

Xiaogang Zhu

Augustine Jian Heng Kuo

Michael James Hurt

Habib Anthony Abouhossein

In Gigibit Ethernet Systems, the Trusted Platform Module (TPM) is designed to provide trust and security to a platform through integrity measurement, protected storage, and other cryptographic functions. The present invention relates to a TPM-LAN chip with separate TPM and LAN power management. The TPM-LAN chip is designed such a way that power is reduced significantly in different power management modes compared to the legacy devices. This is accomplished by turning off certain clocks during certain operating modes.

Apparatus and method for TPM and LAN power management

Switching between communication ports of a notebook is typically accomplished using an off-chip local area network (LAN) switch or an off-chip high speed analog multiplexer. This off-chip component is disadvantageous for several reasons, including: added cost of an additional component; increased overall power consumption because transmit amplitude loss; and reduced cable reach and link performance due to hybrid mismatch and signal distortions. To reduce cost and preserve electrical and networking performance, an integrated switch is provided to multiplex signals of a networking communication chip to multiple network paths.

Integrated switch

In Gigabit Ethernet Systems, the Trusted Platform Module (TPM) is designed to provide trust and security to a platform through integrity measurement, protected storage, and other cryptographic functions. The present invention relates to a TPM-LAN chip with separate TPM and LAN power management. The TPM-LAN chip is designed such a way that power is reduced significantly in different power management modes compared to the legacy devices. This is accomplished by turning off certain clocks during certain operating modes.

Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (&#xbc;) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.

Method and system for direct access memory testing of an integrated circuit

The present invention is directed to methods and systems for scaling receive protocol processing by allowing the network load from a network adapter to be balanced across multiple CPUs based on RSS and/or QoS traffic classification techniques.

Network interface controller with receive side scaling and quality of service

Certain aspects of a system for controlling power for a network interface controller device may comprise a precision voltage comparator that may instantaneously detect ramp up of a main voltage corresponding to a main voltage source in order to control the network interface controller device. A power monitor may detect when a threshold voltage of the main voltage is reached during the ramp up. A main voltage source switch and an auxiliary voltage source switch may switch an output from an auxiliary voltage to the main voltage source without the switches being simultaneously on. The power monitor may determine whether the main voltage is ramping up in excess of a determined rate and if so, may decrease a rate at which the main voltage ramps up. A current limiter and/or the power monitor may monitor and limit an inrush current caused during main voltage ramp up.

Method and system for providing power management for an integrated gigabit ethernet controller

Techniques are disclosed for providing system manageability for computing systems operating under OS-absent conditions. In particular, techniques are disclosed for providing fully functional system management capabilities even when the primary power source for the computing system is disabled. One aspect of the invention provides an ASF-compliant device that selectively supports partial ASF functionality. One aspect of the invention provides an ASF-compliant device that runs ASF firmware that is stored in nonvolatile memory and can be upgraded in the field. One aspect of the invention provides an ASF-compliant device that runs ASF firmware and that can load portions of the ASF firmware into its memory in stages.

Selectively disabling a portion of ASF operations when ASF device is powered by auxiliary power

A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

Integrated gigabit ethernet PCI-X controller

Techniques are disclosed for providing system manageability for computing systems operating under OS-absent conditions. In particular, techniques are disclosed for providing fully functional system management capabilities even when the primary power source for the computing system is disabled. One aspect of the invention relates to a power supply control that facilitates the realization of low power consumption integrated circuit systems. Another aspect of the invention relates to providing fully functional ASF support when operating on auxiliary power. In one embodiment, this is implemented in a local bus adapter/controller that integrates network communication, management, and support features.

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Redondo Beach, CA, United States of America

Andrew Hwang