International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Advanced Micro Devices Corporation

Stmicroelectronics Gmbh

Renesas Electronics Corporation

Other

Tokyo Electron Limited

Globalfoundries U.S. 2 LLC

Auriga Innovations, Inc

Andrew Herbert Simon

Ronald G Filippi

Griselda Bonilla

Naftali Eliahu Lustig

Samuel S Choi

Junjing Bao

Kaushik Chanda

Stephan Grunow

Daniel C Edelstein

Timothy Joseph Dalton

Elbert Emin Huang

Anthony K Stamper

Chih-Chao Yang

Jeffrey P Gambino

Cyprian Emeka Uzoh

Edward Crandal Cooney, Iii

Chao-Kun Hu

Ping-Chuan Wang

Kaushik Arun Kumar

Michael Wayne Lane

Sandra Guy Malhotra

John Anthony Fitzsimmons

Yun-Yu Wang

Thomas W Dyer

Thomas M Shaw

Stephen Edward Greco

Douglas C La Tulipe, Jr

Lee Matthew Nicholson

Mark Hoinkis

Lawrence Alfred Clevenger

Theodorus E Standaert

Sampath Purushothaman

Matthew Earl Colburn

Satyanarayana Venkata Nitta

Vincent James McGahay

Erdem Kaltalioglu

David Lee Rath

Keith Kwong Hon Wong

Injo Ok

Michael Patrick Chudzik

Stephen Mark Rossnagel

Nicole A Saulnier

Fenton Read McFeely

James A Culp

Matthew S Angyal

Mukta G Farooq

Wai-Kin Li

Terry Allen Spooner

Muthumanickam Sankarapandian

William Thomas Motsiff

Kevin W Brew

Christopher Carr Parks

John Jacob Yurkas

Clement Hsingjen Wann

Oleg Gluschenkov

Ruqiang Bao

Soon-Cheon Seo

Katherine Lynn Saenger

Kevin Shawn Petrarca

Koichi Motoyama

Zhengwen O Li

Unoh Kwon

Siddarth A Krishnan

Chandrasekhar Narayan

Shyng-Tsong Chen

Mahadevaiyer Krishnan

Michael F Lofaro

Darryl D Restaino

Dan Moy

Yun Yu Wang

Haining S Yang

Lars W Liebmann

Terence B Hook

Arne Watson Ballantine

Takeshi Nogami

Cyril Cabral, Jr

Hariklia Deligianni

Sanjay C Mehta

Xiao Hu Liu

Richard Anthony Conti

Anna Wanda Topol

Roger Allan Quon

Kwong Hon Wong

Yumiko Kawano

David Edward Kotecki

Tatsuo Hatano

Panayotis Constantinou Andricacos

Hideaki Yamasaki

Sunfei Fang

Atsushi Gomi

Nancy Anne Greco

John A Miller

Andrew Tae Kim

Jonathan Daniel Chapple-Sokol

Erick G Walton

Paul Stephen McLaughlin

Randolph F Knarr

Christopher D Sheraw

Lijuan Zhang

Ronald A Warren

A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.

Confined bridge cell phase change memory

A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.

Phase change memory cell spacer

A semiconductor structure may include a heater surrounded by a second dielectric layer, a projection liner on top of the second dielectric layer, and a phase change material layer above the projection liner. A top surface of the projection liner may be substantially flush with a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Phase change memory cell with a projection liner

A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.

Interconnect structure having subtractive etch feature and damascene feature

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Stacked via structure for metal fuse applications

A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

Forming air gap

Aspects of the present disclosure include a method of forming a semiconductor interconnect structure and the interconnect structure. The method includes etching an opening in a first interconnect dielectric material. The method includes performing a nitridation process that converts the surfaces of the opening into nitride residues, and forms a nitrided interconnect dielectric material surface in the opening. The method includes depositing tantalum to create a tantalum layer on the nitrided interconnect dielectric surface region. The method includes depositing copper to fill the opening and planarizing the surface of the first dielectric material.

Interconnect structure and method of forming

A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the first ILD is above a substrate, and the lower metal line is in the substrate; forming a first barrier layer in the first trench; forming an integrated metal layer (including a first metal line and a first via) on the first barrier layer; forming a first hardmask on the integrated metal layer; forming an isolation trench in the first hardmask and in the first metal line; forming a second barrier layer in the isolation trench; removing a portion of the second barrier layer from a bottom of the isolation trench exposing the first ILD; and forming a second ILD on the second barrier and in the isolation trench, where a bottom of the second ILD is in the first ILD.

Subtractive etch interconnects

A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

Detecting a void between a via and a wiring line

Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.

Insulating a via in a semiconductor substrate

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Back-end electrically programmable fuse

Interconnect structure having substractive etch feature and damascene feature

Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

Fabrication of IC structure with metal plug

Growing community of inventors

Fishkill, NY, United States of America

Andrew Herbert Simon