Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett-packard Development, L.p.

Andrew Harvey Barr

Ken Gary Pomaranski

Dale John Shidla

Ricardo Ernesto Espinoza-Ibarra

Robert William Dobbs

Stephan Karl Barsun

Kirk Michael Bresniker

Jeremy Ian Wilson

Sachin Navin Chheda

Kevin Michael Somervill

Ricard E Espinoza-Ibarra

Thane Michael Larson

Andrew Michael Cherniski

James David Hensley

James Kristian Koch

Irving McKenzie Birmingham

Kenneth Nicholas Konesky

Jacky Tsun-Yao Chang

Gary Logan

A computer system provides for both lock-step and free-step processor modes, allowing for an effective tradeoff between performance and data integrity.

Computing with both lock-step and free-step processor modes

A processor can write its state to an external state cache. Thus, in the event of a processor failure, the stored state can be read and assumed, either by the original processor or another processor. Thus, a process can be resumed from the stored state rather than reconstructed from initial conditions.

External state cache for computer processor

An electronic system has independently coolable first and second zones. The electronic system includes a first zone having a first zone fan and a plurality of first zone connectors for connecting electronic modules and a second zone having a second fan zone and a plurality of second zone connectors for connecting electronic modules. A module manager is also provided for communicating with the first and second zone connectors and with the first and second zone fans. The module manager can independently control the speed of the first and second zone fans based upon operational parameters received from the first and second zone connectors.

System fan management based on system loading options for a system having replaceable electronics modules

A computer system comprising a processor, a memory, and a memory controller coupled to the processor and the memory is provided. The memory controller comprises a first cache and a cache control. The cache control is configured to cause a portion of the memory to be copied into the first cache. The cache control is configured to cause first information to be provided from the first cache to the processor in response to receiving a read transaction from the processor that includes an address in the portion of memory during testing of the portion.

System and method for testing a memory

A computer system that includes a processor, a memory controller coupled to the processor, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the memory controller, a first expansion slot coupled to the first I/O controller, and a test module card coupled to the first expansion slot wherein the test module card is configured to cause tests to be performed on the memory using direct memory access (DMA) is provided.

System and method for testing a memory with an expansion card using DMA

One embodiment disclosed relates to a high-availability cluster apparatus having a plurality of computing nodes and a hardware interface configured to connect to each of said nodes. The internode connections are coupled to the hardware interface to communicate node status signals between said nodes. A node is removable from being connected to the hardware interface without interrupting a topological continuity of the internode connections. Other embodiments are also disclosed.

High-availability cluster node removal and communication

One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.

CPU register diagnostic testing

Embodiments of the invention provide a method and apparatus for selecting a primary resource in a redundant subsystem. In one method embodiment, the present invention receives a list of available resources for a redundant subsystem. Additionally, the available resources are tested and results of the testing are generated. Then, the primary resource is selected for the subsystem based on the results of the testing.

Method and apparatus for selecting a primary resource in a redundant subsystem

Embodiments of the invention provide a method and apparatus for automatically evaluating and allocating resources in a cell based system. In one method embodiment, the present invention receives a request to generate a cell based system of resources. A list of allocatable resources having corresponding evaluation data is then accessed. The request for the cell based system is then compared with the list of allocatable resources having corresponding evaluation data. The allocatable resources are then assigned to the cell based system.

Method and apparatus for automatically evaluating and allocating resources in a cell based system

One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple functional units of a same type. The method includes opportunistically scheduling a redundant operation on one of the functional units that would otherwise be idle during a cycle.

Compiler-scheduled CPU functional testing

In a system and method for managing the performance of a bladed computer system, a management blade identifies one or more individual blades in a chassis. The management blade then automatically determines an optimal performance configuration for each of the individual blades and provides information about the determined optimal performance configuration for each of the individual blades to a service manager. Within the service manager, the information about the determined optimal performance configuration is processed and an individual frequency is set for at least one of the individual blades using the information processed within the service manager.

System and method for managing the operating frequency of blades in a bladed-system

The invention includes a device and method providing a return-signal pathway through a circuit board connector. In one embodiment of the invention, a circuit board connector having an integral bypass capacitor provides a return-signal path between the circuit boards without using the ground planes of the circuit boards outside of an area occupied by the connector. The circuit board connector includes first connector reference conductor arranged for coupling with a first circuit-board reference plane, a second connector reference conductor arranged for coupling with a second circuit-board reference plane, and a capacitor coupled between the first and second reference planes.

Connector having a bypass capacitor and method for reducing the impedance and length of a return-signal path

A computer system comprising a processor configured to cause an operating system to be booted, a test module, and a component coupled to the test module and configured to receive a clock input is provided. The test module is configured to cause the clock input to be provided to the component at a first frequency, and the test module is configured to cause a first test to be performed on the component subsequent to the clock input being provided to the component at the first frequency and the operating system being booted.

System and method for testing a component in a computer system using frequency margining

A method for enabling multiple testing devices within a system. The method may include determining whether a first testing device or a second testing device is coupled to the system. Provided the first testing device is coupled to the system, the method may include enabling the first testing device to operate with an interface of the system capable of coupling to a device under test. Provided the second testing device is coupled to the system, the method may include enabling the second testing device to operate with the interface of the system.

Enabling multiple testing devices

One embodiment disclosed relates to a high-availability (HA) cluster system. The cluster includes a plurality of computing nodes and clustering software configured to manage the cluster. In addition, the cluster includes a smart card, including a microprocessor-based system, communicatively connected to each of the nodes. Another embodiment disclosed relates to an apparatus adapted for use with a corresponding node of a high-availability (HA) cluster. The apparatus includes a microprocessor, control software, at least one input channel to receive data from the corresponding node, at least one output channel to send commands to the corresponding node, at least one input link to receive commands from clustering software of the HA cluster, and at least one output link to send information to the clustering software. Other embodiments are also disclosed.

Growing community of inventors

Roseville, CA, United States of America

Andrew Harvey Barr