Altera Corporation

Andrew Hall

Deshanand Pratap Singh

Steven Perry

Richard Louis Price

Jonathan C Park

Gregor Nixon

Alasdair Scott

Chris Dettmar

Larry Kong

Lingli Wang

Nigel Gray

Peter Brookes

A user logic design for a mask-programmable logic device ('MPLD') may be designed on a comparable or compatible user-programmable logic device ('UPLD') and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD&#x2014;i.e., differences between the devices&#x2014;are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

Method for programming a mask-programmable logic device and device so programmed

A method and apparatus are provided to allow co-verification of hardware and software elements asynchronously from a programmable logic device (PLD).

Simulation of hardware and software

A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic device. By suitably adjusting the relative timing of the device elements, the circuit critical path lengths are effectively reduced leading to improved circuit frequency performance. Algorithms are provided for establishing clock skew values that lead to improved circuit performance. The algorithms are incorporated in computer aided design tools to enable automatic optimization of circuit designs.

Programmable logic devices with skewed clocking signals

The processor typically uses address registers having a particular bit width to access lines within an address space. The bit width limits the address space to a particular size. Techniques are provided for expanding the allowed address bit width and the corresponding address space size by using immediate addressing. Mechanisms allow the run time generation of instructions that can access an array of addresses of varying size, providing a way of implementing address spaces that are not limited by the bit width of address registers.

Using run-time generated instructions in processors supporting wider immediate addressing than register addressing

Growing community of inventors

High Wycombe, United Kingdom

Andrew Hall