Lsi Logic Corporation

Lsi Corporation

Andrew Hadley

Jeffrey K Whitt

Carl Edward Gygi

Erik Paulsen

David W So

Paul Jeffrey Smith

William J Schmitz

Adam S Browen

Stuart L Nuffer

Steven Olson

John Grabarek

A method and system for performing diagnostics and validation operations on a device under test uses near natural language commands. A host machine controls the testing either locally or remotely, such as through the Internet. Various options for running a test or battery of tests on the device under test include entering commands through a prompt line on a graphical user interface, reading commands from a file, or manipulating graphical objects representing components or devices and operations on a graphical user interface. A script may serve as a metric to determine the successfulness of a test or battery of tests of the device under test.

Method, system and programming language for device diagnostics and validation

Methods and structure for standardized communication between a test operator, a host system, and an embedded system under test. Test program instructions are designed, written for, and executed on, an embedded system under test in accordance with standard API functions for message exchange. Still further, the invention provides for standards in the user interface to select a desired test, to start the test with defined parameters and to present reply and status information to the test operator. These user interactions are defined in a test configuration language of the present invention and preferably incorporated with the executable image file to define an integral test vehicle file. The present invention thereby reduces test sequence development time by providing standard API functions for message exchange between a host system test application and the system under test and provides for standardized user interaction in a flexible, easily maintained design language.

Methods and structure for improved testing of embedded systems

A data stream is transferred through a parallel data bus while the read or write strobe is adjusted. The resultant data is compared to the original data to detect errors with each data line of the parallel bus. The results are displayed on a grid whereby the characteristics of each line of the data bus may be visually understood. The characteristic image of the performance of the data bus may be used for debugging the bus, as well as for other uses wherein the performance is very highly characterized.

Characteristic image of electrical data bus

The present invention is directed to a method and system for measuring bus frequency. A system suitable for determining bus frequency may include a bus device and a processor. The bus device is suitable for performing an operation and the processor is communicatively coupled to the bus device utilizing a bus. The processor is capable of starting a timer, initiating the bus device to perform a number of operations, receiving an indication that the bus device completed the number of operations, stopping the timer when the indication is received. A bus clock frequency is computed based upon time taken to complete the number of operations as indicated by the timer and the number of operations performed by the bus device.

System and method for measuring bus frequency

The present invention is a bus reset generator capable of asserting a reset upon detection of a desired phase. The bus reset generator may analyze control signals from a bus, and based upon the control signals may determine the current phase of the bus. If the current phase is the desired phase for a reset, then a reset may be asserted. If the current phase is not the desired phase, the bus reset generator may continue to find the desired phase.

SCSI phase specific bus reset generator

A method and system for controlling and normalizing a rate of a process is described. A hidden process is executed a predetermined number of times as a loop value, and a visual process is executed to complete a cycle. The time to complete a cycle is measured, and an updated loop value is calculated. In a subsequent cycle, the hidden process is executed a number of times equal to the updated loop value so that the visual process is executed at a desired rate normalized across all computing platforms, configuration, and performance environments. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Method and apparatus for controlling and normalizing the desired rate of a visual process across different computing platforms and environments

Control signals of an I/O or peripheral bus are sensed during cycles of the bus and information describing bus phases of the signals is derived by sensing the control signals and is stored in a register. During a sampling time period, a processor reads the bus phase information from the register and computes bus activity information by using the bus phase information. The computed bus information is continuously updated and displayed to reflect actual communication activity on the bus occurring substantially in real-time.

Bus monitor and method of gathering bus phase information in real-time

An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in target operation is provided. In another aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in master operation is provided.

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Colorado Springs, CO, United States of America

Andrew Hadley