Infineon Technologies Ag

Qimonda Ag

Infineon Technologies LLC

Andrew Graham

Franz Hofmann

Franz Kreupl

Michael Specht

Wolfgang Rösner

Johannes Kretz

Thomas Schulz

Richard Johannes Luyken

Erhard Landgraf

Wolfgang Hönlein

Robert Seidel

Maik Liebau

Eugen Unger

Johannes Luyken

Georg Stefan Dusberg

The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Vertically integrated field-effect transistor having a nanostructure therein

A nanotube array and a method for producing a nanotube array. The nanotube array has a substrate, a catalyst layer, which includes one or more subregions, on the surface of the substrate and at least one nanotube arranged on the surface of the catalyst layer, parallel to the surface of the substrate. The at least one nanotube being arranged parallel to the surface of the substrate results in a planar arrangement of at least one nanotube. Therefore, the nanotube array of the invention is suitable for coupling to conventional silicon microelectronics. Therefore, according to the invention it is possible for a nanotube array to be electronically coupled to macroscopic semiconductor electronics. Furthermore, the nanotube array according to the invention may have an electrically insulating layer between the substrate and the catalyst layer. This electrically insulating layer preferably has a topography which is such that the at least one nanotube rests on the electrically insulating layer at its end sections and is uncovered in its central section. As a result of the surface of the at least one nanotube being partly uncovered, the uncovered surface of the nanotube can be used as an active sensor surface. For example, the uncovered surface of the nanotube can come into operative contact with an atmosphere which surrounds the nanotube array. The electrical resistance of a nanotube changes significantly in the presence of certain gases. Thus because the nanotube is clear and uncovered, the nanotube array can be used in many sensor applications.

Nanotube array and method for producing a nanotube array

Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.

Floating gate memory cell with a metallic source/drain and gate, and method for manufacturing such a floating gate memory gate cell

An integrated electronic component having a substrate, a metal multilayer system, which is arranged at least on regions of the substrate, and a nonconductive layer, which is arranged on the metal multilayer system and has at least one contact hole, in which at least one carbon nanotube is grown on the metal multilayer system at the bottom of the contact hole. The metal multilayer system includes a high-melting metal layer, a metal separating layer, a catalyst layer, and a final metal separating layer. The high-melting metal layer is composed of at least one of tantalum, molybdenum, and tungsten. The metal separating layer is composed of aluminum, gold, or silver. The catalyst layer is composed of at least one of iron, cobalt, nickel, yttrium, titanium, platinum, and palladium, and a combination thereof. The final metal separating layer, which is arranged above the catalyst layer, is composed of aluminum.

Integrated electronic component

A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell

A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material. Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.

Process for producing a nanoelement arrangement, and nanoelement arrangement

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Munich, Germany

Andrew Graham