Qualcomm Incorporated

Andrew Gordon Summers

Oleg Popov

Philip Jones

Chi-Fung Kwok

William Daniel Connolley

Georgios Mylonas

Bahareh Siasi

An apparatus is disclosed that implements phase-locked loop (PLL) calibration. In an example aspect, the apparatus includes a PLL and a signal extraction path. The PLL includes an error determiner with an error output node and a loop filter with a filter input node and a filter output node. The filter input node is coupled to the error output node. The PLL also includes a voltage-controlled oscillator (VCO) with a VCO input node. The VCO input node is coupled to the filter output node. The PLL further includes a PLL tap node coupled between the filter output node and the VCO input node. The signal extraction path includes at least one switch, with the signal extraction path coupled to the PLL tap node.

Phase-locked loop (PLL) calibration

Certain aspects of the present disclosure generally relate to apparatus and techniques for wireless communication. One example apparatus generally includes an antenna terminal, an amplifier, a matching network coupled between the antenna terminal and an output of the amplifier, a first voltage envelope detector coupled to a node between the antenna and the matching network, and a current detection circuit coupled to the amplifier.

System for voltage standing wave ratio (VSWR) measurement

A mixer termination circuit for a downconverter mixer includes a diplexer circuit coupled to an output of the downconverter mixer. The diplexer circuit is configured to separately terminate a sum component present in an output signal of the downconverter mixer and a difference component present in the output signal of the downconverter mixer.

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Lawshall, United Kingdom

Andrew Gordon Summers