Wind River Systems, Inc.

Andrew Gaiarsa

Maarten Koning

Thierry C Preyssler

Felix Burton

Vincent Hue

Kevin McCombe

Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of processors executing an operating system, the operating system including a processor local storage mechanism, wherein each processor accesses data unique to the processor based on the processor local storage mechanism. Each of the plurality of processors of the system may have controlled access to the resource and each of the processors is dedicated to one of a plurality of tasks of an application. The application including the plurality of tasks may be replicated using the processor local storage mechanism, wherein each of the tasks of the replicated application includes an affinity to one of the plurality of processors.

Method and system for a CPU-local storage mechanism

The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

System and method for operating system aware low latency interrupt handling

A non-transitory computer-readable storage medium storing a set of instructions that are executable by a processor. The set of instructions, when executed by one or more processors of a multi-processor computing system, causes the one or more processors to perform operations including initiating a first processor of the multi-processor computing system with an operating system image of an operating system, the operating system image including a predetermined object map, initiating a second processor of the multi-processor computing system with the operating system image, placing a plurality of system objects with corresponding processors according to the predetermined object map, receiving a triggering event causing a change to the predetermined object map and relocating one of the system objects to a different one of the processors based on the change to the predetermined object map.

Method and system for reconfigurable virtual single processor programming model

A computer system is provided comprising a core operating system and a system space having a number of memory locations. The core operating system creates a number of protection domains to partition the system space. Each of the partitions includes a partition operating system and a partition user application. Each partition operating system provides resource allocation services to the respective partition user application within the partition.

Two-level operating system architecture

A computer system and method for operating a computer system is provided which comprises a core operating system and a system space having a number of memory locations. The core operating system is arranged to create a number of protection domains to partition the system space into a core operating system space and a plurality of partitions. A partition operating system, a partition user application, and a partition alarm handler is provided in each partition. Each partition operating system provides resource allocation services to the respective partition user application within the partition. An alarm dispatcher and a system alarm handler is provided in the core operating system space. The alarm dispatcher is configured to receive alarms and to dispatch the alarms to one of the alarm handlers.

Health monitoring system for a partitioned architecture

A method for controlling priority inheritance in a computer system is described, the method including testing a priority inheritance variable associated with a task, and lowering the current priority of a task when testing the priority inheritance variable indicates that the task holds no resources that are involved in a priority inheritance.

Growing community of inventors

Carp, Canada

Andrew Gaiarsa