National Semiconductor Corporation

Wireless Logic, Inc.

Andrew G Varadi

Charles E Boettcher

Thomas Klein

Daniel Babitch

John A Reed

Joel A Karp

James Wong

Walid H Maghribi

A cordless system comprises a laptop computer with a modem connected to a modem data port on a cordless telephone handset. A direct sequence spread spectrum RF link is established between the cordless telephone handset and a base station. Both the telephone network and a desktop computer with a modem are connected to the base station. When the cordless telephone handset detects that the laptop computer wants to go off-hook, a selection signal is also sent by the cordless telephone handset to the base station to indicate whether the call is to be directed to the telephone network or the desktop computer. When the base station detects that the desktop computer wants to go off-hook, a selection signal is also sent by the desktop computer to the base station to indicate whether the call is to be directed to the telephone network or over the RF link to the laptop computer. Incoming calls from the telephone network are directed to the desktop computer by the base station with a ring indication going to the cordless telephone handset. If the laptop computer answers the ringing, the cordless telephone handset indicates an off-hook condition to the base station and the base station routes the incoming call over the RF link to the cordless telephone handset and the laptop computer.

Data and voice cordless telephone system

This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.

Method for making a semiconductor capacitor

A process performed by the manufacturer for testing integrated circuits (ICs) to insure better quality and higher reliability thereof and to eliminate the need for incoming inspection and board level testing by the chip customer. In the embodiment disclosed, in-process testing, wafer-probe testing, die separation, packaging, and one by one assembly line testing of the digital memory ICs for catastrophic failures all proceed according to conventional techniques. A large number of the ICs are then plugged into high-temperature, high signal integrity PC storage cards, each adapted for interconnecting the ICs in row-column arrays to form a memory board. The storage cards are mounted within an environmental chamber and are operatively coupled to corresponding PC driver cards mounted externally of the chamber. Next, accelerated dynamic burn-in of the ICs takes place. The PC storage cards are constructed to electrically isolate groups of the ICs so that if an IC in one group has a shorted input, the ICs in the remaining groups will still receive the appropriate dynamic signals to ensure burn-in thereof. Thereafter long functional/pattern testing of the ICs with continuous error logging occurs while the ICs are still mounted in the chamber. Finally the PC storage cards are removed from the chamber and those ICs which have logged either hard or soft errors are separated. The remaining good ICs are subjected to one by one short functional testing to determine compliance with data sheet specs. After quality control testing, the good ICs are shipped to the chip customer who can safely assemble them into user systems without performing the usual customer level incoming inspection and board level testing.

Process of performing burn-in and parallel functional testing of

Method of making integrated semiconductor structure having an MOS and a

This disclosure relates to an MOS or FET memory array that uses a single voltage source (i.e., 5 volts) and operates basically as a static memory array rather than as a dynamic memory array that requires the gates of the MOS devices of the memory array to be periodically refreshed to restore or refresh the memory states contained therein. Each of the memory cells of the memory array contains four MOS devices that are cross-coupled into a flip-flop type of memory cell. All of the memory cells connected to a common word line are also connected to a common return line to which is connected a single resistor and a single large MOS or FET device. The large MOS device is turned on during the active operation of the memory array (during write and read operations) and is turned off during the standby operation of the memory array. The resistor functions to insure that some current flow takes place, during the standby operation, from all the memory cells connected to the common return line in order to maintain the data states ('1' or '0') in each of the memory cells.

Quasi-static MOS memory array with standby operation

This disclosure relates to an MOS random access memory array which utilizes a very small memory cell having a single MOS device and a small size, high capacitance, semiconductor capacitor device connected together to form one bit or memory cell of an MOS dynamic, random access memory array. Preferably, either the source or drain region of the MOS device is connected to the semiconductor portion of the semiconductor capacitor device which is of the electrode-insulator-semiconductor type. The semiconductor capacitor has a very high capacitance due to the use of a very shallow arsenic (N type) implanted region within a boron (P type) implanted region so that the PN junction formed is located where the concentration of Boron impurities is high thereby increasing the capacitance of the semiconductor capacitor. For each memory cell of the memory array, one of the active regions of the MOS device, for example, the source region, is connected to a Bit/Sense line of the memory array. The semiconductor portion of the semiconductor capacitor is connected to the drain region of the MOS device and the electrode plate of the semiconductor capacitor device that is not connected to the drain region of the MOS device is connected to a word line which word line is the next adjacent word line of the MOS random access memory array. The gate of the MOS device is connected up to the word line for that MOS device.

MOS random memory array

In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a '0' or a '1' accessed to one of the bit line portions from an addressed memory cell to be read out of the memory. A high input impedance amplifier is provided between the respective bit line portion and the respective input terminal of the sensing amplifier for isolating (buffering) the stray capacitance of the sensing amplifier circuit from the capacitance of its bit line. Switchable restore circuitry bypasses each of the isolating line amplifiers for the purposes of restoring electrical potentials read out of the addressed memory cells. In a preferred embodiment, the buffer line amplifiers comprise source follower amplifiers.

Growing community of inventors

Saratoga, CA, United States of America

Andrew G Varadi