Raytheon Company

Andrew G Toth

Christopher L Fletcher

Jerry R Cripe

Le Thanh Pham

The present invention concerns, in part, a method for fabricating a silicon PIN detector component wherein three handle wafers are bonded to the wafer at varying points in the fabrication process. The utilization of three handle wafers during fabrication significantly ease handling concerns associated with what would otherwise be a relatively thin and fragile wafer, providing a stable and strong base for supporting those portions of the wafer that will constitute the PIN detector component. In a variant of the present invention, the third handle wafer comprises an optical element transparent in the wavelength of interest.

Method for fabricating a high performance PIN focal plane structure using three handle wafers

A PIN detector device () is fabricated on a substrate (). The substrate () includes a handle wafer portion (), an implanted oxide layer (), a backside contact layer () and an active wafer portion (). The substrate () serves as a foundation to increase stability and facilitate handling during fabrication of electrical circuitry () on a surface of the active wafer portion (). After the electrical circuitry fabrication processing is substantially complete, the handle wafer portion () and implanted oxide layer () are removed to expose the implanted backside contact layer ().

Pin detector apparatus and method of fabrication

Disclosed is a method for producing an array () of p-intrinsic-n light detectors, as is an array produced in accordance with the method. The method includes providing a wafer (); forming a first layer () having a first type of electrical conductivity (e.g., n-type) over a surface of the wafer; forming a second layer () that is an intrinsic layer on the first layer and, for each light detector, implanting or diffusing a region (A) into a surface of the second layer that is opposite the surface on the first layer, the region (A) having a second type of electrical conductivity (e.g., p-type). The method further includes forming an opening or aperture, referred to herein as a V-groove (), through the second layer at least to the first layer; and electrically contacting with a first electrical contact (B,B) the first layer through the V-groove. The method further electrically contacts each of the regions with an associated one of a second electrical contact (A), where the first and second electrical contacts are located on a same, non-radiation receiving surface of the array. In a preferred embodiment the steps of electrically contacting each comprise forming an Indium bump, and further comprise hybridizing the array with a readout integrated circuit (). In the preferred embodiment forming the first layer over the surface of the wafer includes growing a doped epitaxial layer over the surface of the wafer, or it may include implanting the first layer into the surface of the wafer. Forming the second layer on the first layer includes growing an intrinsic epitaxial layer on the first layer to a thickness of, for example 10 microns. The wafer is thinned, either mechanically, or chemically, or by both processes.

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Oxnard, CA, United States of America

Andrew G Toth