Rca Inc.

Harris Corporation

David Sarnoff Research Center, Inc.

Thomson Consumer Electronics S.a.

Harris Semiconductor Patents Inc.

Sarnoff Corporation

Rca Thomson Licensing Corp.

Industrial Technology Research Institute

Ge Company

Electronics Research & Service Org.

Andrew G Dingwall

Victor Zazzu

Roger Green Stewart

Jonathan Lloyd Schepps

Sherman Weisbrod

Fu-Lung Hsueh

Bruce David Rosenthal

Ihor T Wacyk

Ruquiya I Huq

Harry G Erhardt

A column driver for a matrix addressed display such as a liquid crystal display (LCD) is disclosed. The column driver accepts 10-bit inputs, provides 1024 distinct output levels, and is compatible with digital gamma correction by way of, for example, an EPROM lookup table. A complete column driver includes a group of chips which are serially interconnected and receive all the external signals applied in parallel. Only one chip is made active at any instant of time, in order to save power. In each IC, selective polarity inversion of the 10-bit data is carried out before feeding it to a switched capacitor digital to analog converter (CAPDAC) which operates in either a high or low voltage range. All CAPDACs are loaded simultaneously and present a precise output for approximately 95% of each linetime. Each CAPDAC output is connected to a buffer opamp via two CMOS switches which cause the CAPDAC to simultaneously yet transparently change range and allow the opamp buffer to continue driving. The buffer accepts a high impedance, low parasitic input voltage from the CAPDAC array and outputs a low input signal for driving columns with 150-400 pF capacitance. The buffer has an autocalibration circuit that comprises a nested, mini-operational amplifier (opamp) coupled between the output and input of the buffer. The mini-opamp amplifies the balance error produced by the buffer during a calibration interval to provide an output signal which changes the balance point of the buffer amplifier.

Column driver with switched-capacitor D/A converter

Disclosed is a technique for driving a column of pixels implemented using O-LEDs. The technique includes separate, digitally adjustable current sources on each column conductor of the array. For each column, the digitally-programmed current flow terminates with a reference O-LED and a series NMOS transistor forming the input leg of a novel, distributed current mirror. The current is 'mirrored' to the output leg of the distributed current mirror which can service any one of a plurality of active O-LEDs in the column based on a row select signal. In this way, a transistor on the output leg of the current mirror couples its respective O-LED to a source of operational power. The mirrored charge on the gate of the output leg transistor causes it to apply the same current to the active O-LED as was applied to the reference O-LED through the input leg transistor. Additionally, the voltage drop across the NMOS transistor and the reference O-LED is used to charge a capacitor associated with the selected O-LED. The charging of the capacitor, as a result of the digitally-programmed current supplied through the NMOS transistor to the reference O-LED, allows for continuous driving of the active O-LED during a cycle through. Thus, a reference O-LED in conjunction with an NMOS transistor, services all of a plurality of sequentially-loaded rows within each column.

Circuit and method for driving an organic light emitting diode (O-LED)

Matrix addressed LCD display having LCD age indication, and

In an array of a liquid crystal display device having data lines and row select lines, a pair of conductors are provided in a direction transverse to that of the row select lines at opposite sides of the display device. The conductors are capacitively coupled to the row select lines. An amplifier is responsive to a signal generated in one of the conductors from capacitively coupled disturbance signals developed in the row select lines. The amplifier develops an output signal at the other conductor that is also capacitively coupled to the row select lines in a manner that tends to reduce the disturbance signals.

Signal disturbance reduction arrangement for a liquid crystal display

A shift register for scanning a liquid crystal display includes cascaded stages. A given stage is formed with an input transistor switch that is responsive to an output pulse of a stage upstream in the chain of the cascaded stages. An output pulse of the given stage is produced in a pull-up transistor of a push-pull amplifier. A pull-down transistor is responsive to a control signal that tracks a variation of a threshold voltage of the pull-down transistor. A difference between the control signal and the threshold voltage is maintained small in a manner to reduce a change in a conductivity of the pull-down transistor when a drift in the threshold voltage of the pull-down transistor occurs.

Liquid crystal display driver with threshold voltage drift compensation

A liquid crystal display includes pixels that are arranged in columns and rows. Data line drivers responsive to a video signal develop output signals in data lines that correspond with the columns, respectively. An adjustment data line driver is provided. The adjustment data line driver is responsive to a reference DC constant signal at a mid-range of the video signal. An output signal of the adjustment data line driver is coupled to the other data line drivers in a negative feedback manner to compensate for output signal variations in the other data line drivers.

Amplifier with pixel voltage compensation for a display

A level translator includes a latch, a pair of transistors responsive to a switching input voltage and operating in a complementary manner and a pair of zener diodes operating as level shifters. The Zener diodes are coupled between the pair of transistors and the latch. An output transistor is coupled to the latch and produces an output voltage that is level translated with respect to the input voltage. A second embodiment of the invention includes a level translator that produces a first voltage at selectively one of first and second levels and a second voltage at selectively one of third and fourth levels. The first, second, third and fourth levels are different from each other such that in total four different levels are produced. The first and second voltages are coupled to control gates of a pair of transistors operating as a transmission gate.

Level translator with a voltage shifting element

There is described an electronic interrogation and identification (I/I) system in which an interrogator/reader (I/R) unit operates remotely using a microwave beam in conjunction with one or more coded articles. The articles are identified by a unique method and search sequence. As the I/R unit interrogates the articles, one or more of them respond to the I/R unit whenever a code word (data value) sent from the I/R unit matches a code word stored in one or more of the memory positions within the articles. After searching through all of the possible code words and word positions the I/R unit will have identified at least one code word stored in each of the word positions of at least one article. Then combinations of the just-identified code words are matched with the respective stored words of the various articles. After being uniquely identified each article is 'powered-down' on command from the I/R unit and remains inactive so that one-by-one all remaining articles are also identified.

System and method for remote identification of coded articles and the

Electronic system and method for remote identification of coded articles

A differential comparator includes first and second transistors for comparing an input signal to a reference signal during a comparison phase and circuitry for balancing the quiescent currents through the transistors. The circuitry includes a first current source connected to the source of the first transistor, a second current source connected to the source of the second transistor and a selectively enabled impedance means connected between the sources of the two transistors. Prior to each comparison phase the currents through the first and second transistors are balanced (i.e. made approximately equal) by application of equal voltages to the gates of the two transistors and cross-coupling the source potentials of the first and second transistors to control the second and first current sources.

Differential comparator circuit

A set of N digital data bits serially supplied to an input node are converted to an analog voltage by means of N binary weighted capacitors and N switching transistors, one capacitor being associated with one switching transistor for each one of the N digital data bits. Each capacitor is connected between an output node and via the conduction path of its associated switching transistor to a first power terminal. Two transistors are used to selectively sample the N bits of serial data and to couple and store the sampled data on the gates of the switching transistors which are precharged so that the two transistors coupling the serial data only need to conduct in the common source mode. The serial data applied to the gates of the switching transistor is transferred to the N capacitors when a charging voltage is applied to the output node. Following the data transfer onto the binary weighted capacitors, the switching transistors are precharged and, concurrently the N capacitors are connected in parallel to produce an analog voltage corresponding to the serial data.

Switched capacitor D/A converter

A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks. In other embodiments of the invention the ADC is implemented in CMOS technology and the pseudocomparators use ratioed transistor widths and ratioed capacitors to proportionally divide the output signals of the actual comparators in order to generate the interstitial output values. A final embodiment of the invention combines two averaging flash ADCs to form a novel subranging ADC.

Averaging flash analog-to-digital converter

A precise, high speed CMOS track (sample)/hold circuit uses a first circuit leg including four Schottky barrier diodes configured to form a Wheatstone bridge, a second leg with a single n-channel MOS transistor, an essentially constant current source having MOS transistors, a capacitor for holding output signal, and reverse biasing circuitry having MOS transistors for selectively reverse biasing the four diodes. An analog input signal is applied to the cathode of the first diode and to the anode of the second diode. An output signal of the same magnitude and polarity as the input signal is generated at an output terminal (the cathode of the third diode and the anode of the fourth diode) of the circuit when current flows through the first circuit leg. When the current flowing through the first circuit leg is switched to the second circuit leg, the capacitor, which is connected to an output terminal of the circuitry, holds the generated output signal level and the reverse biasing circuitry reverse biases all of the diodes so as to isolate the capacitor from all other components of the circuit.

Precise, high speed CMOS track (sample)/hold circuits

There is disclosed a decoder configuration for a high-speed flash-type analog-to-digital converter which utilizes a plurality of comparators arranged from a first lower order comparator to a last high order comparator based on the particular position of each comparator as coupled to taps of a reference resistance ladder. The measurement point in such a system can be logically decoded by establishing the tap where all comparators below it are low and ideally all comparators above the tap are high. This is implemented in a decoding scheme which implements the test by testing all combinations of three adjacent comparators so that the selected tap is high and the taps immediately above and below it are high and low respectively to therefore detect an HHL sequence. In regard to the present invention, there are included means which will prevent a higher order HHL sequence from appearing when a lower order HHL sequence is detected. In this manner by inhibiting a higher state reading with a lower state reading, one can prevent serious errors which would undesirably cause a 'sparkle' in the decoded output signal.

Decoder error prevention apparatus for use in flash analog-to-digital

A twelve bit analog-to-digital converter uses two banks of 31 capacitors each coupled through separate control circuitry to a five bit analog-to-digital converter with plus or minus 1/2 bit accuracy and two separate eight bit analog-to-digital converters each having plus or minus 1/2 bit accuracy to achieve a frequency of operation from at least several MHz to up to about 40 MHz.

Growing community of inventors

Bridgewater, NJ, United States of America

Andrew G Dingwall