International Business Machines Corporation

Cadence Design Systems, Inc.

Andrew Ferko

Brion L Keller

Bernd K Koenemann

Frank O Distler

Donald Lawrence Wheater

Vikram Iyengar

Robert W Bassett

L Owen Farnsworth

Kenneth Pichamuthu

Leonard O Farnsworth, Iii

Prakash Venkitaraman

Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the 'knee' of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count.

System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count

Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.

System and method for digital logic testing

A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises 'care' bits and 'non-care' bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.

Method and system for reducing test data volume in the testing of logic products

A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises &ldquo;care&rdquo; bits and &ldquo;non-care&rdquo; bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed. The software and/or hardware recover the full test input stimulus data including the fill data from the much more compact source data. The use of a compacted data format for the fill data provides for a high degree of compressibility of the total test input stimulus vector data set. The method for test data reduction combines the compact data representation for the input stimulus data with on-product or off-product compression of the test response data. The response data compression can be accomplished by the use of error-detecting codes, by comparing the responses from several identical products under test. The combination of data compression techniques for both, test input stimulus data and test output response data, results in significantly better overall data reduction.

System for reducing test data volume in the testing of logic products

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Waterbury, VT, United States of America

Andrew Ferko