Qualcomm Incorporated

Ati Technologies Ulc

Ati International Srl

Ati Technologies Inc.

Advanced Micro Devices Corporation

Andrew Evan Gruber

Yun Du

Stephen L Morein

Laurent Lefebvre

Chun Yu

Tao Wang

Lin Chen

Gang Zhong

Eric Demers

Chihong Zhang

Thomas Edwin Frisinger

Milivoje M Aleksic

Donghyun Kim

Zilin Ying

Jonnala Gadda Nagendra Kumar

Vineet Goel

Avinash Seetharamaiah

Alexei Vladimirovich Bourd

Richard Hammerstone

Kalyan Kumar Bhiravabhatla

Liang Li

Baoguang Yang

Fei Wei

Elina Kamenetskaya

Brendon Lewis Johnson

Shambhoo Khandelwal

Yang Xia

Jian Liang

Jian Jiang

Chunhui Mei

Yang Yu

Vinod Chamarty

Andi Skende

Gordon Caruk

Srihari Babu Alla

Indra Laksono

Guofang Jiao

Rahul Gulati

Colin Christopher Sharp

Antonio Asaro

Jay Chunsup Yun

Minjie Huang

Alex Kwang Ho Jong

Brian Hiyin Lee

Hongjiang Shang

Pavan Kumar Akkaraju

Jing Han

Carl K Mizuyabu

Christopher Paul Frascati

Jing Wu

Pramod Vasant Argade

Vishwanath Shashikant Nikam

Edward George Callway

David I Glen

Ankit Kumar Singh

Philip L Swan

Piyush Gupta

John Edward DeRoo

Yongjun Xu

Murat Balci

David Rigel Garcia Garcia

Gaurav Arora

Nigel Terence Poole

Richard J Fuller

Anshuman Saxena

James C Yee

Krishnaiah Gummidipudi

Michael Mantor

Bohuslav Rychlik

Mark Fowler

Christopher Jude Brennan

Skyler Jonathon Saleh

Maxim V Kazakov

Jing Gao

Jeffrey T Brady

Serag Gadelrab

Meghal Varia

Paul Chow

Rexford Alan Hill

Aris Balatsos

Jonathan Wicks

Sudeep Ravi Kottilingal

David A Gotwalt

Daniel Wong

Maurice Franklin Ribble

Feng Ge

Norman Rubin

Mark Sternberg

Sumesh Udayakumaran

Tom Longo

Ravi Jenkal

Tate Hornbeck

Danny H M Cheng

Eduardus Antonius Metz

Christopher L Spencer

Adimulam Ramesh Babu

Vladan Andrijanic

Mark A Sprague

Yunshan Kong

Robert J Simpson

The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.

Rasterization of compute workloads

The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.

Methods and apparatus for selection of rendering modes

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for single pass anti-ringing clamping enabled image processing. A graphics processor may perform a filtering operation on a set of texture samples. The graphics processor may select, during a single sampling operation, a minimum value and a maximum value associated with the set of texture samples during the performance of the filtering operation on the set of texture samples. The graphics processor may adjust, during the single sampling operation, a value of a filtered texture sample associated with the set of texture samples based on the minimum value and the maximum value. The graphics processor may output an indication of the adjusted value of the filtered texture sample.

Single pass anti-ringing clamping enabled image processing

Systems and techniques are provided for accelerated ray tracing. For instance, a process can include obtaining a hierarchical acceleration data structure that includes a plurality of primitives of a scene object and obtaining a respective information value associated with each primitive included in the plurality of primitives. A sort order can be determined for two or more nodes included in a same level of the hierarchical acceleration data structure at least in part by sorting the two or more nodes based on a respective sorting parameter value determined for each respective node of the two or more nodes. Each respective sorting parameter value can be determined based on at least one information value associated with one or more primitives included in a sub-tree of each respective node of the two or more nodes. The hierarchical acceleration data structure can be traversed using the sort order.

Accelerated bounding volume hierarchy (BVH) traversal for ray tracing

The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Performing matrix multiplication in a streaming processor

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.

Runtime mechanism to optimize shader execution flow

Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

Patched shading in graphics processing

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.

Visibility generation improvements in tile based GPU architectures

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.

Run-time mechanism for optimal shader

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.

Fast incremental shared constants

The present disclosure relates to methods and apparatus for graphics processing. For example, disclosed techniques facilitate improving bindless state processing at a graphics processor. Aspects of the present disclosure can receive, at a graphics processor, a shader program including a preamble section and a main instructions section. Aspects of the present disclosure can also execute, with a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program. Additionally, aspects of the present disclosure can distribute the main instructions section and the constant data to a streaming processor for executing the shader program.

Methods and apparatus to facilitate a dedicated bindless state processor

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for compatible compression for different types of image views. A graphics processor may select a first common format of a plurality of common formats for at least one image based on at least one of application data or first metadata associated with the at least one image. The graphics processor may encode the at least one image based on the selected first common format for the at least one image. The graphics processor may select a second common format for the at least one image based on second metadata of the at least one image. The second common format may be identical to the first common format. The graphics processor may decode the at least one image based on the selected second common format for the at least one image.

Compatible compression for different types of image views

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for dynamic wave pairing. A graphics processor may allocate one or more GPU workloads to one or more wave slots of a plurality of wave slots. The graphics processor may select a first execution slot of a plurality of execution slots for executing the one or more GPU workloads. The selection may be based on one of a plurality of granularities. The graphics processor may execute, at the selected first execution slot, the one or more GPU workloads at the one of the plurality of granularities.

Dynamic wave pairing

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for GPU wave-to-wave optimization. A graphics processor may execute a shader program for a first wave associated with a draw call or a compute kernel. The graphics processor may identify at least one first indication for the first wave associated with the draw call or the compute kernel. The graphics processor may store the at least one first indication for the first wave to a memory location. The graphics processor may execute the shader program for at least one second wave associated with the draw call or the compute kernel. The execution of the shader program for the at least one second wave may be based on the shader program for the at least one second wave reading the memory location to retrieve the at least one first indication.

GPU wave-to-wave optimization

Growing community of inventors

Arlington, MA, United States of America

Andrew Evan Gruber