Qualcomm Incorporated

Andrew Edmund Turner

Bohuslav Rychlik

George Patsilaras

Wesley James Holland

Moinul H Khan

Feng Wang

Subbarao Palacharla

Anwar Q Rohillah

Simon Peter William Booth

Jeffrey Shabel

Jeong-Ho Woo

Marta Karczewicz

Wei-Jung Chien

Cheng-Teh Hsieh

Yanru Li

Tao Wang

Matthew Levi Severson

Natan Jacobson

Alain Artieri

Jeffrey Gemar

Vinod Chamarty

Ali Iranli

Hao Liu

Raghu Sankuratri

Prashant Dinkar Karandikar

Kedar Bhole

Clara Ka Wah Sung

Kris Tiri

Engin Ipek

Tarek Zghal

Farrukh Hijaz

Pavan Kumar Thirunagari

Hamza Omar

Goran Goran

Hyung Joon Kim

Ejebagom Ojogbo

A method and apparatus for reducing a memory footprint of compressed data by dynamically allocating and recycling memory pages. The method may include allocating a dedicated subset of the memory pages to a private page pool separate from a main memory such that the dedicated subset of the memory pages is allocatable separately from the main memory, receiving compressed data, allocating at least one physical address of the dedicated subset of the memory pages from the private page pool for the compressed data, and writing the compressed data to the one or more physical addresses.

Systems and methods for dynamically allocating memory pages to enable memory footprint reduction

Systems, devices, apparatus, and methods, including computer programs encoded on storage media, for truncation error signaling and adaptive dither for lossy bandwidth compression are described. A processor may perform a truncation process for data, where the data is associated with display processing, image processing, or the data processing, where the truncation process for the data results in truncated data. The processor may compute a set of truncation error values associated with the truncation process for the truncated data. The processor may generate a set of residual samples for the truncated data. The processor may generate a bitstream based on the set of residual samples for the truncated data and the set of truncation error values associated with the truncation process.

Truncation error signaling and adaptive dither for lossy bandwidth compression

Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Providing content-aware cache replacement and insertion policies in processor-based devices

Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

Space and time cache coherency

Embodiments include methods for image compression and decompression. A sending computing device may determine a type of packing used for a chunk of image data, generate metadata describing the type of packing used for the chunk of image data, pack the chunk of image data according to the determined type of packing, and send the packed chunk of image data and the metadata to a second computing device. A receiving computing device may decode the metadata describing the type of packing used for the chunk of image data, determine the type of packing used for the chunk of image data based on the decoded metadata, and unpack the chunk of image data according to the determined type of packing used for the chunk of image data.

Image compression and decompression

Memory system features may promote cache coherency where first and second memory clients may attempt to work on the same data. A second client cache system may provide a read request for data and associated metadata. The metadata element may be detected in a first client cache system. The first client cache system may write or flush, such as to a system memory, one or more cache lines containing the metadata and associated data and invalidate the flushed cache lines. The second client cache system may receive the data and metadata, such as from the system memory, completing or fulfilling the read request.

Marshalled data coherency

In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture

An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

System and method for intelligent tile-based prefetching of image frames in a system on a chip

Systems and methods for managing coherency in a processing system comprising a memory involve one or more aperture cache coherency (ACC) blocks. The ACC blocks monitor accesses to the memory using aliased addresses, wherein the aliased addresses map to locations in an aliased address domain of the memory. The ACC blocks also monitor accesses to the memory through a functional address aperture using aperture addresses, wherein a function of the aperture addresses map to locations in an aperture address domain of the memory. The ACC blocks are further configured to maintain coherency between one or more of data in a first location of the memory, the first location belonging to the aliased address domain and the aperture address domain; one or more copies of the data accessed using the aperture addresses; or one or more copies of the data accessed using the aliased addresses.

Cache coherence with functional address apertures

Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.

Automatic cache coherency for page table data

Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

Cache line compaction of compressed data segments

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.

Dynamic input/output coherency

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.

Hybrid input/output coherent write

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing asynchronous cache maintenance operations on a computing device, including activating a first asynchronous cache maintenance operation, determining whether an active address of a memory access request to a cache is in a first range of addresses of the first active asynchronous cache maintenance operation, and queuing the first active asynchronous cache maintenance operation as the first asynchronous cache maintenance operation in a fixup queue in response to determining that the active address is in the first range of addresses.

Asynchronous cache operations

Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Growing community of inventors

San Diego, CA, United States of America

Andrew Edmund Turner