Broadcom Corporation

Andrew Du Preez

Bin Liu

Wei Luo

Louis Botha

Frederic Hayem

Shuangquan Wang

Johan (Hendrik) Conroy

Mark Hahm

Severine E Catreux-Erceg

Jun Wu

Thirunathan Sutharsan

Li Fung Chang

Karthik Rajagopalan

Yi Zhou

Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.

Method and system for a programmable interference suppression module

Aspects of a method and system for compensation of interference cancellation delay are provided. In this regard, a wireless communication device may receive one or more signals and may be operable to select, whether dynamically or statically, a processing path for processing the one or more received signals. The selected processing path may comprise one of an interference cancellation processing path and a pass-through processing path. A delay introduced by the pass-through processing path may be approximately equal to a processing delay introduced by the interference cancellation processing path. The one or more received signals may comprise HSDPA signals. The selection of processing path may be based on a measure of interference present in the one or more received signals.

Method and system for compensation of interference cancellation delay

Aspects of a method and system for dynamically programmable serial/parallel bus interface may include performing in a first communication device coupled to a communication bus, attaching communication protocol information to a data signal for each data transaction with one or more other communication devices communicatively coupled to the communication bus. The one or more other communication devices may be controlled utilizing the attached communication protocol information. The communication protocol information may be dynamically adjusted and/or adaptively adjusted. The communication bus may be a serial or parallel communication bus. The serial communication bus may be a two-wire, three-wire, or four-wire bus. The attached communication protocol information comprises a multi-wire protocol, a 3-wire protocol, a Serial Peripheral Interface (SPI) protocol, a System Power Management Interface (SPMI), or an RF Bus protocol.

Method and system for dynamically programmable serial/parallel bus interface

Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

Method and system for a RFIC master

A combined data packing, cipher and multiplexing engine operable to support high speed uplink packet access (HS-UPA) within user equipment (UE) is provided. This combined cipher multiplexing engine includes a master port, a radio link control (RLC) data packer, and a cipher multiplexing processing module. The master port couples to an advanced microprocessor bus architecture (AMBA) high speed buss (AHB) on which control information for the combined cipher and multiplexing engine is provided. The RLC couples to the master port and receives RLC service data units (SDUs) from the AHB. Then the RLC data packer may concatenate or segment RLC SDUs into RLC packet data units (PDUs) which are stored for use by a cipher multiplexing processing module. The cipher multiplexing processing module retrieves the RLC PDU from the RLC PDU buffer and ciphers to produce ciphered data, if cipher is enabled and multiplexes the ciphered/non-ciphered data together with the RLC header, MAC-es header, MAC-e header and enters the multiplexed results to a hybrid automatic repeat request (HARQ) buffer. A protocol stack executed within the UE activates and provides an array on the formation of the RLC PDU, RLC header information to the combined cipher and multiplexing engine for RLC PDU ciphering and medium access control (MAC) multiplexing of the enhanced data transport channel (E-DCH).

High-speed uplink packet access (HSUPA) cipher multiplexing engine

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San Diego, CA, United States of America

Andrew Du Preez