International Business Machines Corporation

Jds Uniphase Corporation

Andrew Douglas Davies

James David Strom

Daniel Lawrence Stasiak

Grant Paul Kesselring

Salvatore Nicholas Storino

Christopher W Steffen

David Michael Friend

Sudipto Chakraborty

John Francis Bulzacchelli

David James Frank

Daniel Joseph Friedman

John Michael Borkenhagen

Andrew Benson Maki

Stanley Everett Schuster

Thomas W Liang

Herschel Akiba Ainspan

Steven John Baumgartner

Robert Russell Williams

Peter William Cook

Timothy Clyde Buchholtz

Dana Marie Woeste

Joel T Ficke

Daniel Guy Young

Frederick Jacob Ziegler

Ann Chen Wu

Jeff Van Tran

Thomas Pham

Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

High frequency AC coupled self-biased divider

Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

Calibrating signal currents in a radio frequency signal generator

A radio frequency (RF) transmission circuit includes an input stage, a current-mode mixer coupled to an output of the input stage, an attenuator coupled to an output of the current-mode mixer, and a matching network coupled to an output of the attenuator. The input stage, current-mode mixer, attenuator, and the matching network are configured in a series stack.

Current-mode frequency translation circuit with programmable gain

A voltage-controlled oscillator comprises a varactor. A capacitance of the first varactor is dependent upon a control voltage. The voltage-controlled also comprises an inductor. The inductor is connected to a center-tap connection. The voltage-controlled oscillator also comprises a power source. The power source is configured to provide a bias voltage to the inductor through the center-tap connection. The voltage-controlled oscillator also comprises a coupling capacitor. The coupling capacitor is located between the inductor and the varactor. The voltage-controlled oscillator also comprises a coupling resistor. The coupling resistor is located between the coupling capacitor and the center-tap connection. The center-tap connection provides the bias voltage to the coupling capacitor through the coupling resistor.

Voltage-controlled oscillator with centertap bias

A method and circuit for implementing a level shifter for translating logic signals to output voltage analog levels, and a design structure on which the subject circuit resides are provided. The circuit includes a level shifter resistor divider string of a plurality of series connected resistors, the level shifter resistor divider string is connected between an analog voltage rail and an analog ground. A plurality of level shifter cascaded inverters are connected between respective resistors of the level shifter resistor divider string and an analog voltage rail and an analog ground. An output of the level shifter is programmed by the level shifter resistor divider string connected to the cascaded inverters.

Implementing cascade level shifter for analog voltage

A system includes a voltage controlled oscillator (VCO) having an adjustable amplitude. The amplitude of the VCO may be adjusted by adjusting voltage level present at a center tap node of an inductor. The VCO may have an adjustable amplitude that may be programmed on a chip-by-chip basis based on a chip parameter, power consumption, or oscillator performance.

VCO selection and amplitude management using center tap inductor

A method and a clock receiver circuit for implementing low jitter and enhanced duty cycle, and a design structure on which the subject circuit resides are provided. The clock receiver circuit accepts single-ended complementary metal oxide semiconductor (CMOS) and differential clock signals. The clock receiver circuit includes input circuitry coupled to a differential pair that biasing a reference clock and allows for single-ended or differential clock signals. The differential pair uses multiple current mirrors for switching the polarity of the input signals to achieve enhanced jitter performance, and cross coupled inverters for retaining signal symmetry.

Implementing clock receiver with low jitter and enhanced duty cycle

A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Variable frequency oscillator with specialized inverter stages

A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.

Unlock mode in source synchronous receivers

The invention relates to a feedback circuit for a transimpedance amplifier, which is typically used for converting an input current from a photodiode into an output voltage. The feedback circuit of the present invention linearizes the transconductance feedback, as the input current signal varies, by providing a constant current source for supplementing the DC feedback current through a bypass transistor, thereby reducing a variation in the low frequency cut off.

Transimpedance amplifier with linearized transconductance feedback

An apparatus and method for externally managing data within an asynchronous pipeline. The asynchronous pipeline over which control is sought includes a data path and a control path. In accordance with the method of the present invention, a data tag value is assigned to the data prior to its entry into the asynchronous pipeline. The data tag value is sent into the control path at the same time the data is sent into its data path such that the data tag value passes through the asynchronous pipeline in parallel with the data to which it is assigned. At a given stage within the asynchronous pipeline, the data tag value is compared with a control tag value, and only in response to the data tag value matching the control tag value is the data permitted to pass to the next stage within the asynchronous pipeline.

Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages

The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits

A zero-detection circuit is provided. The zero-detection circuit includes a plurality of transistor stacks. Each transistor stack includes an input transistor and a clocked transistor. Each of the plurality of input transistors receives a data input. An intermediate node is connected to the input transistor stacks. An output stage is coupled to the intermediate node providing an output. The output stage includes a bit selection control circuit receiving a bit selection signal. The bit selection control circuit provides a zero level output of the output stage responsive to a predefined bit selection signal. The transistor stacks comprise silicon-on-insulator (SOI) transistors.

High speed microprocessor zero detection circuit with 32-bit and 64-bit modes

A circuit and a method to realize a programmable delay between two adjacent signal paths, each having a different timing domain. In a preferred embodiment, each signal path is a stage of domino logic and the programmable delay is positioned at the boundary to adjust the timing between the two stages. The delay is programmed depending upon the value of an input signal to be either a static delay and hence part of the first stage of domino logic; or a dynamic delay to be part of a subsequent stage of domino logic. Critical paths can easily be balanced after fabrication, either at wafer test or once the circuit is mounted on an integrated chip and then tested, with the programmable gate as disclosed herein.

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Rochester, MN, United States of America

Andrew Douglas Davies