Texas Instruments Corporation

National Semiconductor Corporation

Andrew Derek Strachan

Alexei Sadovnikov

Venkat Raghavan

Douglas Brisbin

Henry Litzmann Edwards

Natalia Lavrovskaya

Vladislav Vashchenko

James Robert Todd

Terry Dyer

Gregory Keith Cestra

Dening Wang

Gang Xue

Peter J Hopper

Christopher Boguslaw Kocon

Binghua Hu

Constantin Bulucea

Philipp Lindorfer

Yuri Mirgorodski

Xiaoju Wu

Roozbeh Parsa

Tathagata Chatterjee

Saurabh Desai

Steven Loveless

Jim McGinty

Dhanoop Varghese

Sheldon D Haynie

A method to fabricate a transistor includes implanting dopants into a semiconductor to form a drift layer having majority carriers of a first type; etching a trench into the semiconductor; thermally growing an oxide liner into and on the trench and the drift layer; depositing an oxide onto the oxide liner on the trench to form a shallow trench isolation region; implanting dopants into the semiconductor to form a drain region in contact with the drift layer and having majority carriers of the first type; implanting dopants into the semiconductor to form a body region having majority carriers of a second type; forming a gate oxide over a portion of the drift layer and the body region; forming a gate over the gate oxide; and implanting dopants into the body region to form a source region having majority carriers of the first type.

Transistors with oxide liner in drift region

Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

Drain extended transistor

Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a plurality of resistor unit cells arranged in an array, each resistor unit cell formed within the semiconductor substrate and including a top contact. A conductive layer located over the semiconductor substrate electrically connects to a subset of the top contacts.

Vertically-constructed, temperature-sensing resistors and methods of making the same

In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.

Dynamic biasing to mitigate electrical stress in integrated resistors

Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material; a first contact coupled to the first doped region; a second contact opposite the first contact coupled to the second doped region; and an isolation trench to circumscribe the third doped region.

A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1&#xd7;10cm, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

Low dynamic resistance low capacitance diodes

A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.

Split-gate lateral extended drain MOS transistor structure and process

The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

Method of forming a biCMOS semiconductor chip that increases the betas of the bipolar transistors

Method of forming a BICMOS semiconductor chip that increases the betas of the bipolar transistors

In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

Schottky diode integrated into LDMOS

A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Method of forming a robust, modular MIS (metal-insulator-semiconductor) capacitor with improved capacitance density

An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Data retention in a single poly EPROM cell

A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer forms contact pads for a thin film resistor.

Growing community of inventors

Santa Clara, CA, United States of America

Andrew Derek Strachan