Arm Limited

Andrew David Tune

Sean James Salisbury

Daniel Adam Sara

Peter Andrew Riocreux

Alistair Crone Bruce

Guanghui Geng

Arthur Brian Laughton

Jamshed Jalal

Edward Martin McCombs, Jr

Robin Hotchkiss

George Robert Scott Lloyd

Bruce James Mathewson

Phanindra Kumar Mannava

Mark David Werkheiser

Rahul Mathur

Julian Jose Hilgemberg Pontes

Alessandro Grande

Andrew Brookfield Swaine

David Hennah Mansell

Akshay Kumar

Simon Charles Watt

Brett Stanley Feero

Cyrille Nicolas Dray

Zheng Xu

David Joseph Hawkins

Lionel Belnet

Hsin-Yu Chen

Timothy Charles Mace

Peter James Aldworth

Simon Crossley

Pierre Michel Broyer

Lorenzo Di Gregorio

Phani Raja Bhushan Chalasani

Saira Samar Malik

Rakesh Raman

Gaurav Kumar

Daniel Sara

Ian David Andrews

A control circuit is configured to receive a stream of addresses associated with cache lookup requests resulting from execution of a workload by a data processing system. The control circuit includes a cache miss monitor and a cache hit monitor both coupled to a controller. The cache miss monitor determines a number of reoccurring misses as a difference between the number of addresses in the stream of addresses that miss in the cache and the number of such addresses that are unique. The cache hit monitor includes a moment circuit configured to determine first and second frequency moments addresses in the stream of addresses that hit in the cache. The controller controls the data processing system based on the number of reoccurring misses and the first and second frequency moments. A bypass mechanism of the cache may be controlled, for example.

Method and apparatus for reduction of recurring cache misses

An apparatus comprises an non-inclusive cache () configured to cache data and coherency control circuitry (). The coherency control circuitry is configured to look up the non-inclusive cache in response to a coherent access request from a first requestor (). In response to determining that the coherent access request can be serviced using data stored in a matching entry of the non-inclusive cache, the coherency control circuitry references snoop-filter information associated with the matching entry to determine whether the first requestor can use the data stored in the matching entry without waiting for a response to a snoop of a coherent cache ().

Coherency control

A method for write operations to memory include starting write operations for writing n words in a same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and closing the write operations for the writing of the n words during a final clock cycle, whereby the n words are written in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. The write circuitry performing the aforementioned operations can also perform write operations for a single word in two clock cycles.

Increased throughput for writes to memory

A transaction handling device comprises transaction handling circuitry to handle a transaction request for a data processing transaction, the transaction request having an associated identifier such that at least an aspect of processing for each of a set of transaction requests having the same identifier must be performed in the order of issue of that set of transactions; and detection circuitry to detect the state of an indicator associated with the identifier to indicate whether that identifier relates to more than one concurrently pending transaction request.

Managing transaction request identifiers and indicators to control or bypass in-order handling of transaction requests

Data storage circuitry has entries to store data according to a data storage technology supporting non-destructive reads, each entry associated with an error checking code (ECC) and age indication. Scrubbing circuitry performs a patrol scrubbing cycle to visit each entry of the data storage circuitry within a scrubbing period. On a given visit to a given entry, the scrubbing operation comprises determining, based on the age indication associated with the given entry, whether a check-not-required period has elapsed for the given entry, and if so performing an error check on the data of the given entry using the ECC for that entry. The error check is omitted if the check-not-required period has not yet elapsed. The check-not-required period is restarted for a write target entry in response to a request causing an update to the data and the error checking code of the write target entry. The check-not-required period is restarted for a read target entry in response to a request causing the data of a read target entry to be non-destructively read and subject to the error check.

Patrol scrubbing cycle for data storage circuitry

Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

Circuitry and method

A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

Burst read with flexible burst length for on-chip memory

An apparatus comprises a cache comprising a plurality of cache entries, and cache replacement control circuitry to select, in response to a cache request specifying a target address missing in the cache, a victim cache entry to be replaced with a new cache entry. The cache request specifies a partition identifier indicative of an execution environment associated with the cache request. The victim cache entry is selected based on re-reference interval prediction (RRIP) values for a candidate set of cache entries. The RRIP value for a given cache entry is indicative of a relative priority with which the given cache entry is to be selected as the victim cache entry. Configurable replacement policy configuration data is selected based on the partition identifier, and the RRIP value of the new cache entry is set to an initial value selected based on the selected configurable replacement policy configuration data.

Cache replacement control

There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.

Apparatus and method for buffered interconnect

A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.

Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols

A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response to the issue of the one or more data handling instructions to the one or more given nodes.

Data processing

Data processing apparatus comprises one or more transaction issuing devices configured to issue data processing transactions to be handled by a downstream device and to receive a completion acknowledgement in respect of each completed transaction; each transaction issuing device having associated transaction regulator circuitry configured to allow that transaction issuing device to issue transactions subject to a limit on a maximum number of outstanding transactions, an outstanding transaction being a transaction which has been issued but for which a completion acknowledgement has not yet been received; in which the downstream device is configured to issue an indication to a transaction issuing device, to authorize a change by the transaction regulator circuitry of the limit applicable to outstanding transactions by that transaction issuing device.

An interconnection network is provided for managing data transfer between a plurality of nodes of an integrated circuit. The interconnection network has at least one transmission path originating from an upstream location of the interconnection network, each transmission path being arranged to transmit data blocks from the upstream location to an associated downstream location within that transmission path. Digest generation circuitry is used to generate digests for data blocks, and fault detection circuitry provided in association with the upstream location is arranged to determine presence of a fault condition in the interconnection network. The digest generation circuitry is arranged to generate an upstream digest for a given data block at the upstream location, and to generate a corresponding downstream digest for the given data block at the associated downstream location. The fault detection circuitry is arranged to receive upstream digests from the upstream location and corresponding downstream digests received via a return path from each downstream location, and to determine presence of the fault condition based on a comparison of each upstream digest with its corresponding downstream digest.

Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream location

An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.

Data access request specifying enable vector

An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

Growing community of inventors

Dronfield, United Kingdom

Andrew David Tune