Semiconductor Components Industries, LLC

Intel Corporation

Andrew David Talbot

Nicholas Paul Cowley

Stephen J Spinks

Isaac Ali

Colin Leslie Perry

William L Barber

Keith Pinson

Mark S Mudd

Chi Man Kan

Alan J Martin

Matthew T Aitken

Stephen James Spinks

Keith D Jones

Mukesh Rao Engla Syam

Colin Mair

An image sensor may include an image sensor pixel array. The image sensor pixel array may include active image sensor pixels and non-active image sensor pixels. A line of peripheral image sensor pixels may be coupled to a corresponding interconnect structure via a pixel signal path. The pixel signal path may include portions that overlap pass-through pixels and a keep-out region beyond an edge of the image sensor pixel array. Multiple interconnect structures may connect the image sensor pixel array implemented on a first integrated circuit die to pixel control and readout circuitry on a second integrated circuit die.

Image sensor signal path routing

An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may include a respective plurality of column output lines. Each column output line may be coupled to a respective subset of the imaging pixels in that column of imaging pixels. Each plurality of column output lines for a given column may be coupled to readout circuitry. Each group of column output lines may share a single respective sample and hold circuit and a single respective analog-to-digital converter. Alternatively, each group of column output lines may have one sample and hold circuit per column output line and each group of column output lines may share a single respective analog-to-digital converter. Alternatively, each group of column output lines may have one sample and hold circuit per column output line and may have one analog-to-digital converter per column output line.

Image sensors with multiple column output lines per column

An image sensor may include an image sensor pixel array. The image sensor pixel array may include active image sensor pixels that generate image data based on incident light and reference pixels that are optically black for generating reference data for noise compensation. Sets of reference pixels in the same row may be coupled to respective shared readout paths in a source follower binning configuration. The shared readout path may be could to downstream readout circuits. The use of shared readout paths for the reference pixels can reduce the number of reference pixel readout paths. If desired, pixel circuitry may be implemented on a first die, while readout circuitry and at least a portion of the reference pixel readout paths may be implemented on a second die mounted to the first die.

Reference pixel column readout

An image sensor may be implemented by mounting a first die to a second die. The first die may include an image sensor pixel array having active pixels and non-active pixels, while the second die may include pixel control and readout circuitry that are coupled to the image sensor pixel array via inter-die connections. The image sensor pixel array may have pixel columns in excess of corresponding column readout paths in the pixel readout circuitry and/or pixel rows in excess of corresponding sets of row control paths in the pixel control circuitry. A select set of inter-die connections may be implemented to provide connections between a desired set of pixel columns and the limited number of column readout paths and to provide connections between a desired set of pixel rows and the limited number of sets of row control paths.

Expanded image sensor pixel array

Various embodiments of the present technology provide a method and apparatus for an image sensor. In various embodiments, the apparatus provides a driver circuit connected to a plurality of electrically distinct pixel groups to provide the pixel groups with a control signal. A delay measurement circuit is connected to the driver circuit and at least one of the pixel groups to measure a time delay of the control signal. A row control circuit is connected to the delay measurement circuit to receive the measured time delay and, in turn, deliver, via the driver circuit, the control signal to all pixel groups in a single row substantially simultaneously.

Methods and apparatus for an image sensor

An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of tiles in a reticle set. Multiple instantiations of a same circuitry block on a given tile may be patterned and formed on the image sensor die. The image sensor die may include circuitry configured to enable testing of one or more instantiations of the same circuitry block. The image sensor die may include memory circuitry for storing indications of a functional instantiation of the multiple instances and may use the functional instantiation for normal operation.

Stitched integrated circuit dies

An image sensor may be implemented using a stitched image sensor die. The stitched image sensor die may be formed from a step and repeat exposure process using a set of physical tiles in a reticle set. The physical tiles may include a center tile forming pixel circuitry on the image sensor die and peripheral tiles forming non-pixel circuitry on the image sensor die. Each of the physical tiles may be sized based on an integer multiple of a virtual unit tile. As such, the physical tiles may have dimensions that are not required to be an integer multiple of the smallest physical tile. The step and repeat exposure process may use the unit lengths of the virtual unit tile to properly position the die relative to the processing tools.

An image sensor may include a pixel array, row control circuitry, and column readout circuitry. The row control circuitry may operate the pixel array in a global shutter mode of operation. In particular, timing control circuitry may provide global timing clock signals associated with a global photodiode reset event and a global photodiode charge transfer event to row driver circuitry providing control signals to each row in the array. Each driver circuitry may include a time delay circuit that delays the global timing clock signal by different amounts across the rows. Therefore, these global events may be offset on a per-row or per-row group basis, thereby mitigating power surges associated with global events. Further, by offsetting the global photodiode reset and charge transfer events using the same delay for a given row, the same global integration time may be preserved across different rows.

Systems and methods for mitigating global event power surge in image sensors

An image sensor may include a pixel array having pixels arranged in rows and columns, column readout circuitry, and control circuitry. Column readout circuitry may include corresponding readout circuits each coupled to a corresponding column path for a respective column of pixels. The readout circuits may each include signal processing circuits such as correlated double sampling circuitry and analog-to-digital converter circuitry. To reduce peak-to-average power ratio, during the signal processing operations for each pixel row, the control circuitry may control the signal processing circuits to perform time-domain multiplexing across the pixel columns to activate the signal processing circuits at varied times within the row time. If desired, the pattern of time-domain multiplexing may be varied across the signal processing operations for different pixel rows and/or for different image frames.

Image sensors with reduced peak power

An imaging device may have an array of image sensor pixels arranged in rows and columns and column readout circuitry coupled to the array. The rows of pixels may receive drive signals from row driver circuitry, and the drive signals may be sent from timing circuitry based on the locations of rows within the array. In particular, rows closer to the readout circuitry may require less settling time and therefore be driven faster than the rows further from the readout circuitry. All of the rows may be driven in a single direction, or the array of pixels may have a cut, in which case rows above the cut may be driven up and rows below the cut may be driven down. A frame buffer may be used to store the signals generated by the rows of pixels and may account for the asynchronous read out of image data.

Image sensors with variable read out circuitry

A dual mode voltage regulator according to one embodiment includes a passive regulator circuit, a switching regulator circuit, and a controller circuit configured to determine parameters of an external select input. The controller is configured to selectively couple, on a cold boot up, either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load based on the determination of parameters.

Dual mode voltage regulator with reconfiguration capability

A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal.

Dual mode voltage regulator with dynamic reconfiguration capability

A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.

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Chieveley, United Kingdom

Andrew David Talbot