Cadence Design Systems, Inc.

Fujitsu Microelectronics Limited

Andrew David Beckett

Arnold Ginetti

Ian Juso Dedic

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with efficient cell cloning. A cell instance corresponding to multiple similar cell instances in a view of an electronic design may be identified, where the cell instance is instantiated from a master parameterized cell. An analysis engine may be configured at least by associating a parameter of the master parameterized cell with multiple different parameter values respectively corresponding to the multiple similar cell instances. An analysis result including respective metric values corresponding to the multiple similar cell instances may be generated at least by performing an analysis that sweeps across the multiple different parameter values.

Methods, systems, and computer program product for characterizing an electronic design with efficient cell cloning

Disclosed herein are embodiments of systems, methods, and products providing technology database independent pcells to be seamlessly customized and implemented in a yet unknown IC package library. In particular, the technology database independent pcells may have a code to execute callback functions to retrieve the package library name of the parent cells hosting the pcells. Based upon the library name, the pcell code may access the technology files stored in the technology database of the package library of the parent cells to retrieve the layer name, layer number, the design resolution, and/or other information such as design rule information of the parent cells hosting the pcells. Based on the layer number, the resolution, and/or other information the pcells can configure for themselves correct layout geometry without any input from a circuit designer.

Technology database independent components for integrated circuit package

An analog-to-digital converter (ADC) operates repetitively to perform a series of conversion cycles. A comparator (9) receives an analog input signal (V.sub.IN) and compares it with an analog comparison signal produced by a digital-to-analog converter (5). A successive-approximation register circuit (22) holds a digital trial signal value and uses it to control the value of the analog comparison signal in each conversion cycle so as to perform up to two comparisons per cycle, thereby to produce digital data that has a first value ('+1') when the input signal value is greater than a first comparison value (V.sub.C1) and that has a second value ('-1') when the input signal value is less than a second comparison value (V.sub.C2) and that in all other cases has a third value ('0'). The first comparison value (V.sub.C1) is set higher than the trial signal value determined for use in the cycle concerned, and the second comparison value is set lower than that trial signal value. Each comparison value differs from the trial signal value by the same predetermined amount. The successive-approximation register circuit (22) adjusts the trial signal value in each cycle in dependence upon the digital data produced in the cycle concerned so as to tend to bring that value into closer correspondence with the input signal value. Such an ADC can employ the same analog circuits (5,7,9) as a conventional successive-approximation ADC but can operate at higher speeds because errors in the decisions made in one conversion cycle are, within reasonable limits, corrected automatically in subsequent conversion cycles.

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Wokingham, United Kingdom

Andrew David Beckett