Micron Technology Incorporated

Intel Corporation

Andrew D Proescholdt

Nathan Joseph Sirocka

Trismardawi Tanadi

Yihua Zhang

Gerard A Kreifels

Paolo E Mangalindan

Jianfei Lei

Luigi Pilolli

Guan Wang

Ravi Annavajjhala

Lucia Botticchio

Alec W Smidt

Boubekeur Benhamida

Luca Di Loreto

Rosario D'esposito

Operations include generating a voltage level associated with a digital signal corresponding to a write operation associated with one or more memory cells of a memory device, comparing the voltage level to a reference voltage level to generate a comparison result, generating based on the comparison result, a command to adjust a duty cycle associated with the digital signal; and adjusting the duty cycle associated with digital signal based on the command.

Write duty cycle calibration on a memory device

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.

Error correction code event detection

A high-speed voltage level shifter. A transistor () may be connected to high voltage (VPP) and may act as a source of a limited current to a first node (), and a driver () connected to the first node may provide a level-shifted output signal (VOUT) to a memory control input line of a memory cell (). A plurality of series-connected transistors (A&#x2013;N) may be connected between a second node (A) and a circuit ground, each transistor may have an input connected to a corresponding control signal (VIN-A to VIN-N) from a control circuit (). A transistor () may be connected between the first node and the second node in a source-follower configuration and may have an input connected to a bias voltage (VBIAS) which may limit the voltage at nodeA, so transistorsA&#x2013;N may be low-voltage, high speed transistors.

Voltage level shifter

Growing community of inventors

Rancho Cordova, CA, United States of America

Andrew D Proescholdt