USA As Represented by Secretary of the Navy

University of California

Northrop Grumman Systems Corporation

Andrew D Koehler

Travis J Anderson

Karl D Hobart

Francis J Kub

Marko J Tadjer

Tatyana I Feygelson

Mark Goorsky

Michael Anthony Mastro

Virginia D Wheeler

Samuel Graham, Jr

Geoffrey M Foster

Zhe Cheng

Luke Yates

Tingyu Bai

Lunet E Luna

Yekan Wang

Jordan D Greenlee

Vincent Gambin

Joshua D Caldwell

Alan G Jacobs

Ioulia Smorchkova

Bradford B Pate

Boris N Feygelson

Gregory Todd Lewis

Daniel G Georgiev

Matthew Porter

Rajinder S Sandhu

Mona A Ebrish

Raghav Khanna

Michael Robert Hontz

David Shahin

Jeff McKay

Eugene I Imhoff

Prakash Pandey

Tolen Michael Nelson

A hybrid edge termination structure and method of forming the same. The hybrid edge termination structure in accordance with the invention is based on a junction termination extension (JTE) architecture, but includes an additional Layer of guard ring (GR) structures to further implement the implantation of dopants into the structure. The hybrid edge termination structure of the invention has a three-Layer structure, with a top Layer and a bottom Layer each having a constant dopant concentration in the lateral direction, and a middle Layer consisting of a plurality of spatially defined alternating regions that exhibit the electrical properties of either the top or bottom layer. By including the second layer, a discretized varying charge profile can be obtained that approximates the varying charge profile obtained using tapered edge termination but with easier manufacturing and lower cost.

Multi-layer hybrid edge termination for III-N power devices

A light controlled semiconductor switch (LCSS), method of making, and method of using are provided. In embodiments, a vertical LCSS includes: a semiconductor body including a photoactive layer of gallium nitride (GaN) doped with carbon; a first electrode in contact with a first surface of the semiconductor body, the first electrode defining an area through which light energy from at least one light source can impinge on the first surface; and a second electrode in contact with a second surface of the semiconductor body opposed to the first surface, wherein the vertical LCSS is configured to switch from a non-conductive off-state to a conductive on-state when the light energy impinging on the semiconductor body is sufficient to raise electrons within the photoactive layer into a conduction band of the photoactive layer.

Low resistance photoconductive semiconductor switch (PCSS)

Light controlled switching modules are provide. In embodiments, a light controlled switching module includes: a housing; a light controlled semiconductor switch mounted to the housing, the light controlled semiconductor switch including a semiconductor body; at least one light source mounted to the housing in a spaced relationship from the light controlled semiconductor switch and positioned to direct light emitted from the at least one light source toward the semiconductor body; and first and second electrodes mounted to the housing and connected to the light controlled semiconductor switch, wherein the first and second electrodes are configured to have variable resistance between the first and the second electrode.

Light controlled switch module

A method for growing polycrystalline diamond films having engineered grain growth and microstructure. Grain growth of a polycrystalline diamond film on a substrate is manipulated by growing the diamond on a nanopatterned substrate having features on the order of the initial grain size of the diamond film. By growing the diamond on such nanopatterned substrates, the crystal texture of a polycrystalline diamond film can be engineered to favor the preferred &#x3c;110&#x3e; orientation texture, which in turn enhances the thermal conductivity of the diamond film.

Diamond on nanopatterned substrate

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.

Heterojunction devices and methods for fabricating the same

A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.

Diamond air bridge for thermal management of high power devices

An method of annealing by: providing a substrate having a III-nitride, sapphire, silicon, diamond, gallium arsenide, or silicon carbide surface; depositing a layer of a transition metal nitride directly on the surface; and annealing the substrate at at least 900&#xb0; C. in an oxygen-free environment. An article having: a substrate having a III-nitride, sapphire, silicon, diamond, gallium arsenide, or silicon carbide surface; and a layer of a transition metal nitride directly on the surface.

Transition metal-bearing capping film for group III-nitride devices

A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.

Method of making a graphene base transistor with reduced collector area

Systems and method are provided for depositing metal on GaN transistors after gate formation using a metal nitride Schottky gate. Embodiments of the present disclosure use a 'diamond last' process using thermally stable metal nitride gate electrodes to enable thicker heat spreading films and facilitate process integration. In an embodiment, the 'diamond last' process with high thermal conductivity diamond is enabled by the integration of thermally stable metal-nitride gate electrodes.

Diamond on III-nitride device

Systems and methods are provided that enable the production of semiconductor devices having a metal nitride layer in direct contact with a semiconductor layer to form a Schottky diode, such as a TiN gate on an AlGaN/GaN high electron mobility transistor (HEMT). Metal nitrides offer exceptional thermal stability and a lower diffusion coefficient. Technology enabled by embodiments of the present disclosure improves the reliability of GaN-based microwave power transistors.

Metal nitride alloy contact for semiconductor

Passivated AlGaN/GaN HEMTs having no plasma damage to the AlGaN surface and methods for making the same. In a first embodiment, a thin HF SiN barrier layer is deposited on the AlGaN surface after formation of the gate. A thick HF/LF SiN layer is then deposited, the thin HF SiN layer and the thick HF/LF Sin layer comprising bi-layer SiN passivation on the HEMT. In a second embodiment, a first thin HF SiN barrier layer is deposited on the AlGaN surface before formation of the gate and is annealed. Following annealing of the first SiN layer, the gate is formed, and a second HF SiN barrier layer is deposited, followed by a thick HF/LF SiN layer, the three SiN layers comprising tri-layer SiN passivation on the HEMT.

Damage-free plasma-enhanced CVD passivation of AlGaN/GaN high electron mobility transistors

A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.

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Alexandria, VA, United States of America

Andrew D Koehler