Intel Corporation

Amazon Technologies, Inc.

Andrew D Henroid

Paul S Diefenbaugh

Eugene Gorbatov

Krishnakanth Venkata Sistla

Eliezer Weissmann

Guy M Therien

Barnes Cooper

Efraim Rotem

Ankush Varma

Jeremy J Shrall

Anil Aggarwal

Alon Naveh

Inder M Sodhi

Dheeraj R Subbareddy

Robert E Gough

David A Koufaty

Ganapati Srinivasa

Paolo L Narvaez

Mishali Naik

Andrew J Herdrich

Eric C Samson

David W Browning

James G Hermerding, Ii

Russell Jerome Fenger

Tod F Schiff

Vasudevan Srinivasan

Ashish V Choubal

Neil W Songer

Scott D Hahn

Guy G Sotomayor

Gaurav Khanna

Paul Brett

Abirami Prabhakaran

Bret L Toll

Jason W Brandt

Stephen Anthony Fischer

Michael Mishaeli

Kevin Moore

Hisham Shafi

Rinat Rappoport

Brian J Rundle

Darin J Klaas

Akhil Ramachandran

Matthew Rives Vegas

Oron Lenz

Sanjeev S Sahagirdar

Michael A Rothman

Mohan J Kumar

Tsung-Yuan Charles Tai

Ren Wang

Alexander W Min

Jr-Shian Tsai

Bryant E Bigbee

Sarathy Jayakumar

Mark Doran

Jose Andy Vargas

Mesut A Ergin

Bruce L Fleming

Faraz A Siddiqi

Neelam Chandwani

Michael Calyer

Sameer Abhinkar

Ruchika Singh

Russel J Fenger

Guarav Khanna

Techniques for on-demand issuance of private keys for encrypted video transmission are described. A video processing service of a provider network receives a request from a computing device outside the provider network to begin video processing of video data generated by a video source device outside the provider network. The video processing service sends instructions to a video encoding device associated with the video source device to establish the connection for video transmission. The video processing service sends an encryption key to the video encoding device, and sends a decryption key to a video decryption engine. Subsequently, the video processing service receives video data from the video source device, via the video encoding device.

Video encoding device for use with on-demand issuance private keys

On-demand issuance private keys for encrypted video transmission

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

Dynamically updating logical identifiers of cores of a processor

The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

Collaborative processor and system performance and power management

In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

Supercapacitor-based power supply protection for multi-node systems

In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Techniques and system for managing activity in multicomponent platform

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Computing platform interface with memory management

In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.

Performing dynamic power control of platform devices

Growing community of inventors

Portland, OR, United States of America

Andrew D Henroid