Alliance Semiconductor Corporation

Andrew D Daniel

Spencer H Greene

Thomas Alexander

William N Schnaitter

A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.

48-bit wide memory architecture addressing scheme reconfigurable for

A divider/multiplier circuit (10) is disclosed. In a divider mode, numerator terms are coupled to a normalizer (14) which generates normalized numerator values and corresponding numerator exponent values therefrom. Denominator terms are coupled to a look-up normalizer (20) which generates normalized denominator inverse values and corresponding denominator exponent values therefrom. The numerator and denominator exponent values are summed in an adder circuit (18) to generate a sum exponent value. The normalized numerator and inverse denominator values are multiplied in a multiplier circuit (16) to generate a normalized quotient value. The normalized quotient value is denormalized according to the sum exponent value. In a multiply mode of operation first and second multiplicands are coupled to the multiplier circuit (16). In a high precision divide mode, a sequence of numerator and inverse denominator values are coupled to the multiplier circuit (16) to generate a sequence of partial product terms. The partial product terms are accumulated in a high precision loop (24) to provide a high precision division value. Negative multiplicands and numerator values are handled by a leading absolute value generator (12) which generates the absolute value of the multiplicand or numerator value. A trailing signed value generator (22) additively inverts the product or quotient if the multiplicand or numerator value was negative.

Divider/multiplier circuit having high precision mode

A method and apparatus of displaying video and graphics data together in a computer graphics display using only the memory needed for the graphics display includes determining the location of the video window in the frame buffer, writing video data to the portion of the frame buffer bounded by the video window. During the raster scan of the frame buffer, if the raster position is within the video window, video data are read from the video data addresses within the video window. When the displayed video window position is changed, the video data are moved accordingly.

Method and apparatus for displaying a video window in a computer

A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).

Display refresh system having reduced memory bandwidth

A display control circuit controls the outputs of the three video DACs of an RGB monitor on a window-to-window basis to enable the display of motion video and text on the same screen with different brightness and/or tint. A digital overdrive signal, synchronized to the video DAC digital inputs, is used to enable added DAC elements for the pixels in the video windows only. Stored digital instructions determine how many and which added DAC elements are enabled by the overdrive bit(s). By storing different instructions for each of the three video DACs, the circuit may also provide window-dependent tint control. By increasing the number of bits of digital data synchronized to the digital DAC inputs, the stored instructions may be reduced or eliminated. In this case, each of several windows may be set to differing brightness and tint levels. As many different values of brightness and tint may be available as desired by increasing the number of synchronized input enabling bits and the number and strength of the added DAC elements.

Window-dependent brightness/tint control for video digital-to-analog

A method and apparatus for dynamically regrouping display memory chips to efficiently implement 8-bit, 16-bit, and 24-bit per pixel display solutions is provided. The invention permits the implementation of 24-bit per pixel solutions in which 24-bit pixels do not straddle addressable regions, but without requiring the use of a unused byte of display memory per 24-bit pixel.

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San Jose, CA, United States of America

Andrew D Daniel