International Business Machines Corporation

Nvidia Corporation

Microsoft Technology Licensing, LLC

Silicon Graphics, Incorporated

Andrew D Bowen

David C Tannenbaum

David Conrad Tannenbaum

Robert W Gimby

Henry Packard Moreton

David L Dignam

Dominic Acocella

Christopher James Goodman

Robert Spencer Horton

Robert Tamlyn

Thomas H Kong

Gregory C Buchner

Timothy J Ebbers

Thomas Melvin Ogletree

Randall L Henderson

David S Warren

Jeffrey B Moskal

Dawn Maxon

Michael Timothy Jones

Nathaniel David Naegle

Vimal S Parikh

Mark S Peercy

Paul Mark Schanely

Craig Michael Wittenbrink

John Milligan Airey

Gregory M Eitzmann

Nathan R Hiltebeitel

Michael A Aranda

Leland D Richardson

Jakob Nebeker

Remi Simon Vincent Arnaud

Steven Gregory Foster, Jr

Paul A Simoncic

Jeffrey Scott Spencer

James Bowman

Daniel T Chian

A method and system for graphics instruction fetching. The method includes executing a plurality of threads in a multithreaded execution environment. A respective plurality of instructions are fetched to support the execution of the threads. During runtime, at least one instruction is prefetched for one of the threads to a prefetch buffer. The at least one instruction is accessed from the prefetch buffer if required by the one thread and discarded if not required by the one thread.

Method and system for non stalling pipeline instruction fetching from memory

The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.

Culling before setup in viewport and culling unit

Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerouted from the second data stream into the first data stream; a token inserted in the second data stream identifies a position of the rerouted element. The modified streams are transmitted by the two buses. A receiving circuit reinserts the rerouted data element into the second data stream at the sequential position identified by the placeholder token.

System and method for delivering multiple data streams via multiple buses

A graphics processing subsystem includes a vertex processing unit that allows vertex shader programs to arbitrarily access data stored in vertex texture maps. The vertex processing unit includes a vertex texture fetch unit and vertex processing engines. The vertex processing engines operate in parallel to execute vertex shader programs that specify operations to be performed on vertices. In response to a vertex texture load instruction, a vertex processing engine dispatches a vertex texture request to the vertex texture fetch unit. The vertex texture fetch unit retrieves the corresponding vertex texture map data. While the vertex texture fetch unit is processing a vertex texture request, the requesting vertex processing engine is adapted to evaluate whether instructions that follow the vertex texture load instruction are dependent on the vertex texture map data, and if the instructions are not dependent on the vertex texture map data, to execute the additional instructions.

Vertex processing unit supporting vertex texture mapping

The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.

Cull before attribute read

Accordingly, embodiments of the present invention provide circuits, methods, and apparatus that improve utilization of storage buffers by overwriting data in them as soon as the data is no longer needed. An exemplary embodiment employs a counter to add each time a particular unit of data is needed by a circuit. The counter also subtracts each time the data is actually used by the circuit. When the counter reaches zero, upstream circuitry is checked to see if a command allowing the particular data to be overwritten has been issued. If it has, the command is not waited for, rather the data may be overwritten immediately. Embodiments of the present invention may also make use of one level of indirection to mask physical storage buffer locations from upstream circuitry. In this way, utilization can be improved.

Storage buffers with reference counters to improve utilization

A method for tiling multiple displays to generate a large area display of moving data. Specifically, one embodiment of the present invention includes a system for generating a large area display of moving data. The system comprises a display image generator for rendering pixels of an image to be displayed as the large area display. Furthermore, a plurality of tiled image projectors are coupled to the display image generator to receive pixel data and to generate the large area display. The plurality of tiled image projectors comprise at least two image projectors. A first image projector which performs a first type of raster scanning sequence to display a first portion of the pixel data. Moreover, a second image projector which performs a second type of raster scanning sequence to display a second portion of the pixel data, wherein the second type of raster scanning sequence is different than the first type of raster scanning sequence. Therefore, the present invention provides a method and system for tiling multiple image projectors to generate a large area display of moving images and data which is free of visual defects or anomalies. As such, the present invention is able to produce large area displays exhibiting more realistic and lifelike images thereby improving the viewing experience of the viewer.

Method for tiling multiple displays to generate a large area display of moving data

One aspect of the invention is a method for displaying extended range pixel values. The method includes the step of receiving a plurality of image pixel values each with at least one associated data value. The method also includes the steps of sending at least one of the plurality of image pixel values to a first display device ( ) having a maximum display value; and sending at least one of the plurality of image pixel values exceeding maximum display value to a second display device ( ). In a further embodiment, the at least one associated data value may be at least one of the group consisting of a pixel intensity, a color, and a location of the pixel value.

Extended range pixel display system and method

A pull-model system and method provides display data over a network to a plurality of display devices having the same or different video format requirements. Utilization of image memory bandwidth is balanced between the plurality of display devices. Based on image memory bandwidth requirements for the plurality of display devices, a bandwidth allocation table is generated to indicate a servicing priority for the display devices. A plurality of requests for pixel data are received and stored in a request buffer. The requests are then serviced in an order indicated by the bandwidth allocation table.

System and method for load balancing in a multi-channel graphics system

A method for interfacing to ultra-high resolution output devices. The basic idea of the present invention is to subdivide an ultra-high resolution display screen into narrow strips or column subsections, thereby enabling the mapping of multiple pixel interfaces to it. In this manner, the full pixel display is completely mapped. As such, multiple image generators are able to create in parallel their specific narrow strip of the full pixel display using view frustum culling, which is known by those of ordinary skill in the art. It should be appreciated that an interface in accordance with the present invention is not tied tightly to a scanning architecture. As such, this keeps a level of abstraction between the image generator and the many different types of display devices. Furthermore, since this interface is by design a rasterization interface, more image generators and less expensive image generators can be used for driving the display device. Moreover, by abstracting the interface, it necessitates a line buffer within the display device, thereby removing the need for transferring the pixel data in actual real-time.

Method for interfacing to ultra-high resolution output devices

A system and method for the phase alignment of signals of arbitrary relative frequency are described. A phase difference detector detects a phase difference between a first signal pulse and a corresponding second signal pulse. A phase comparator compares this detected phase difference to a calculated expected phase difference, to produce an error signal proportional to the difference. The clock generator adjusts the frequency of one of the signals by an amount based on the error signal, in order to phase align the first signal to the second signal. In a preferred embodiment, the first and second signals are video signals with a common frame rate and different line rates.

System and method for locking disparate video formats

A method and apparatus for synchronizing the execution of a sequence of graphics pipelines is provided. For a representative embodiment a sequence of graphics pipelines are connected in a daisy-chain sequence. Each pipeline operation can be controlled to operated in one of two modes. The first is a local mode where the pipeline outputs its own digital video data. The second is a pass-through mode where the pipeline outputs digital video data received from preceding graphics pipelines. The pipelines are configured to allow an application executing on a host process to select the next pipeline that will enter local mode operation. The pipeline that is selected to enter local mode operation asserts a local ready signal when it is ready to begin outputting its digital video information. Each of the pipelines monitors the state of a global ready signal. When the global ready signal becomes asserted it means that the pipeline that is selected to enter local mode operation is ready. It also means that all other pipelines that are configured to work in parallel with the sequence of pipelines are ready. At this time, selected the selected pipeline enters local mode operation. The remaining pipelines in the sequence either enter or remain in pass-through mode operation.

Method and apparatus for synchronizing graphics pipelines

The present invention provides a method, a device, and a system for performing gamma correction on a set of pixel data based on a gamma correction curve table. The gamma correction curve table includes a specified total number of intensity levels associated with gamma corrected pixel values with one intensity level per pixel value. The method includes partitioning the gamma correction curve table into N segments such that each of the N segments is associated with a set of intensity levels from the specified total number of intensity levels. A plurality of intensity levels is selected for each of the N segments such that significant banding effects are not visible to the human eye between an adjacent pair of the selected intensity levels. The gamma corrected pixel values are stored for each of the N segments such that each of the plurality of selected intensity levels functions as an index to the associated gamma corrected pixel values. Gamma correction is performed on the set of pixel data by accessing a stored pixel value in one of the N segments in response to the pixel data to generate gamma corrected pixel data.

Floating point gamma correction method and system

A computer graphics system having a hyperpipe architecture. Multiple rendering pipes are coupled together through a hyperpipe network scheme. Each of the rendering pipes are capable of rendering primitives for an entire frame or portions thereof. This enables multiple rendering pipes to process graphics data at the same time. A controller coordinates the multiple rendering pipes by sending requests to the appropriate rendering pipes to retrieve the pixel data generated by that particular pipe. It then merges the pixel data received from the various rendering pipes. A single driver then draws the three-dimensional image out for display.

Apparatus and method for utilizing multiple rendering pipes for a single 3-D display

An operation for combining multiple video streams permits combining any number of overlay images and base images regardless of processes performed upon one or more of the images. Specifically, where the base images are dynamically sized and resized to provide a constant frame rate (despite varying frame complexity), the process similarly treats overlay images and even other base images. In the dynamic sizing process, a rendering time is compared to high and low water marks. During dynamic resizing, two double buffering operations and a synchronization operation are performed. After dynamic sizing and resizing, the resulting resized images are combined together, regardless of the frame rate of the individual images. Consequently, multiple video streams at varying frame rates are combined at a constant frame rate.

Growing community of inventors

San Jose, CA, United States of America

Andrew D Bowen