Intel Corporation

Andrew Cunningham

Eliezer Tamir

Niall D McDonnell

Bruce Richardson

Andrey Chilikin

Debra Bernstein

John Joseph Browne

Chris MacNamara

William G Burroughs

Hugh Wilkinson

Patrick Fleming

Peter P Waskiewicz, Jr

Johannes Berg

Jonathan Kenny

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

Jr-Shian Tsai

David Sonnier

Stephen R Van Doren

Edwin Verplanke

Pierre Laurent

Namakkal N Venkatesan

Yipeng Wang

James T Clee

Narender R Vangati

Changzheng Wei

Jerry Pirog

David Hunt

Joseph R Hasting

Niall Power

Te Khac Ma

Gage Eads

Kevin Devey

Stephen Miller

Jamison D Whitesell

An Yan

Bradley A Burres

Tomasz Kantecki

Stephen Doyle

Mark D Gray

Jonas Svennebring

Christopher MacNamara

Bjorn Topel

Carl-Oscar Montelius

Stephen T Palermo

Yadong Li

Anjali Singhai Jain

Sailesh Bissessur

Alexander J Leckey

Brendan Ryan

Chih-Jen Chang

Eoin Walsh

Naveen Lakkakula

Sean Harte

Michael A O'Hanlon

Naru Dames Sundar

Chris Macnamara

Rory Sexton

Nemanja Marjanovic

Richard Guerin

Charitra Sankar

Ralph Castro

Barak Hermesh

Examples described herein relate to a network interface device that includes circuitry, configured to perform encryption of data, generate one or more packets from the encrypted data, cause transmission of the one or more packets with the encrypted data, manage reliability of transport of the transmitted one or more packets with the encrypted data, and share protocol state information between a host system and the network interface device using connectivity based on user space accessible queues.

Transport and cryptography offload to a network interface device

Methods, apparatus, systems and articles of manufacture are disclosed to control execution of tasks in a computing system. The methods, apparatus, systems and articles of manufacture include at least one storage device and at least one processor to, execute instructions to at least obtain a request to perform an inverse operation on a data flow, the data flow previously transformed during a forward operation, determine a first processor core that executed the forward operation, the data flow including an identifier of the first processor core, and transmit the data flow to a second processor core to perform the inverse operation.

Methods and apparatus to control execution of tasks in a computing system

Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.

Extending Berkeley packet filter semantics for hardware offloads

Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

Technologies for providing efficient detection of idle poll loops

Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

Software-defined networking data re-direction

Extending Berkeley Packet Filter semantics for hardware offloads

Extending berkeley packet filter semantics for hardware offloads

Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Techniques for processor queue management

A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.

Lazy increment for high frequency counters

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Examples include techniques for a configuration mechanism of a virtual switch. Example techniques include monitoring a database including parameter to configure a virtual switch at a computing platform hosting a plurality of virtual machines or containers. Changes to one or more parameters may cause changes in allocations of computing resources associated with supporting the virtual switch.

Techniques for a configuration mechanism of a virtual switch

Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

Technologies for demoting cache lines to shared cache

An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.

Techniques for cache delivery

Growing community of inventors

Ennis, Ireland

Andrew Cunningham