Kla Tencor Corporation

Kla Corporation

Andrew Cross

Kaushik Sah

Allen Park

Martin Plihal

Antonio Mani

Brian Duffy

Moshe E Preil

Roel Gronheid

Arpit Yati

Jagdish Chandra Saraswatula

Wing-Shan Ribi Leung

Shivam Agarwal

Sayantan Das

Mike VonDenHoff

Sandip Halder

Process window qualification (PWQ) layouts can be used to determine a presence of a pattern anomaly associated with the pattern, patterning process, or patterning apparatus. For example, a modulated die or field can be compared to a slightly lower offset modulated die or field. In another example, the high to low corners for a particular condition or combination of conditions are compared. In yet another example, process modulation parameters can be used to estimate criticality of particular weak points of interest.

Process window qualification modulation layouts

A characterization system for inspecting or performing metrology on a layer within a semiconductor stack is disclosed. The system includes an imaging sub-system configured to acquire image data from a semiconductor stack including one or more layers. The semiconductor stack includes a metal layer having a thickness between 0.5 and 10 nm deposited on a layer of the semiconductor stack to form a reflective surface on the layer. The system includes a controller. The controller is configured to receive image data of the reflective surface on the layer of the substrate stack and identify one or more defects or one or more structures within the layer based on illumination reflected from the reflective surface.

Sensitivity improvement of optical and SEM defection inspection

An inspection-sensitive additive can improve inspection of photoresist on semiconductor wafers. The inspection-sensitive additive can be used to stain the photoresist or can be deposited as a layer on the photoresist. The inspection-sensitive additive can have a k-value that is greater than 20% larger than a photoresist k-value of the photoresist layer for an inspection wavelength between 120 nm and 950 nm.

Inspection sensitivity improvements for optical and electron beam inspection

A wafer topography measurement system can be paired with a scanning electron microscope. A topography threshold can be applied to wafer topography data about the wafer, which was obtained with the wafer topography measurement system. A metrology sampling plan can be generated for the wafer. This metrology sampling plan can include locations in the wafer topography data above the topography threshold. The scanning electron microscope can scan the wafer using the metrology sampling plan and identify defects.

Guided scanning electron microscopy metrology based on wafer topography

A stochastic calculation engine receives inputs from a semiconductor inspection tool or semiconductor review tool. The stochastic calculation engine determines abnormal locations and pattern variation from the inputs and determines stochastic failures from the inputs. An electronic data storage unit connected with the stochastic calculation engine can include a database with known stochastic behavior and known process metrology variations. The stochastic calculation engine can flag stochastic features, determine a failure rate, or determine fail probability.

Using stochastic failure metrics in semiconductor manufacturing

Methods and systems fir identifying nuisances and defects of interest (DOIs) in defects detected on a wafer are provided. One method includes acquiring metrology data for the wafer generated by a metrology tool that performs measurements on the wafer at an array of measurement points. In one embodiment, the measurement points are determined prior to detecting the defects on the wafer and independently of the defects detected on the wafer. The method also includes determining locations of defects detected on the wafer with respect to locations of the measurement points on the wafer and assigning metrology data to the defects as a defect attribute based on the locations of the defects determined with respect to the locations of the measurement points. In addition, the method includes determining if the defects are nuisances or DOIs based on the defect attributes assigned to the defects.

Identifying nuisances and defects of interest in defects detected on a wafer

Information from metrology tools can be used during inspection or review with a scanning electron microscope. Metrology measurements of a wafer are interpolated and/or extrapolated over a field, which creates modified metrology data. The modified metrology data is associated with defect attributes from inspection measurements of a wafer. A wafer review sampling plan is generated based on the defect attributes and the modified metrology data. The wafer review sampling plan can be used during review of a wafer using the scanning electron microscope.

Metrology guided inspection sample shaping of optical inspection results

A weak pattern identification method includes acquiring inspection data from a set of patterns on a wafer, identifying failing pattern types on the wafer, and grouping like pattern types of the failing pattern types into a set of pattern groups. The weak pattern identification method also includes acquiring image data from multiple varied instances of a first pattern type grouped in a first group, wherein the multiple varied instances of the first pattern type are formed under different conditions. The weak pattern identification method also includes comparing images obtained from common structures of the instances of the first pattern type to identify local differences within a portion of the first pattern type. Further, the weak pattern identification method includes identifying metrology sites within the portion of the first pattern type proximate to a location of the local differences within the portion of the first pattern type.

Method and system for weak pattern quantification

A system, method, and computer program product are provided for systematic and stochastic characterization of pattern defects identified from a fabricated component. In use, a plurality of pattern defects detected from a fabricated component are identified. Additionally, attributes of each of the pattern defects are analyzed, based on predefined criteria. Further, a first set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be systematic pattern defects, and a second set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be stochastic pattern defects. Moreover, a first action is performed for the determined systematic pattern defects and a second action is performed for the determined stochastic pattern defects.

System, method and computer program product for systematic and stochastic characterization of pattern defects identified from a semiconductor wafer

A design aware system, method, and computer program product are provided for detecting overlay-related defects in multi-patterned fabricated devices. In use, a design of a multi-patterned fabricated device is received by a computer system. Then, the computer system automatically determines from the design one or more areas of the design that are prone to causing overlay errors. Further, an indication of the determined one or more areas is output by the computer system to an inspection system for use in inspecting a multi-patterned device fabricated in accordance with the design.

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Cheshire, United Kingdom

Andrew Cross