Sgs-thomson Microelectronics Limited

Stmicroelectronics Gmbh

Andrew Craig Sturges

David May

Nathan Mackenzie Sidwell

Michael David May

Glenn Ashley Farrall

Mark Hill

Hendrick-Jan Agterkamp

Andrew Michael Jones

Catherine Louise Barnaby

Bruno Fel

Andrew Keith Betts

Brian Foster

A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

Cache system

A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

Computer system and method for fetching, decoding and executing instructions

A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Cache system for concurrent processes

A method of automated generation of a set of design data defining a system model from an architecture database which is configured to hold in an electronic storage medium architectural parameters wherein each architectural parameter is defined by a primary key field and a set of fields holding subsidiary data relating to the primary key, the method comprising, reading the primary key for each architectural parameter, generating in an electronic storage medium a structured definition entry of the architectural parameter in an electronically readable format, the structured definition entry being associated with an identification field defining the parameter, and loading the primary key into the identification field and the subsidiary data into the structured definition file, and wherein the structured definition entry takes the form of a programming definition of the architectural parameter in a modelling language.

Maintenance of a system model

A computer system has compact instructions avoiding the need for redundant bit locations and needing simple decoding. Logic circuitry is arranged to respond to an instruction set comprising a plurality of selectable instructions of different bit lengths. Each instruction is based on a format of predetermined bit length and a predetermined sequence of instruction fields each of a respective predetermined bit length. Some instructions omit a selected one of the fields and include an identifier of less bit length than the omitted field to indicate which field is omitted. Thus this bit length of the instruction is compressed. The logic circuitry is operable to restore the omitted field on execution of the instruction.

Computer instruction compression

The transmission of interrupts is described where the interrupt is represented at a peripheral device by the electrical level of a conductor but where it is conveyed to a receiving module by way of a message packet routed along a routing path. According to one aspect, the message packet includes the identification of the peripheral device which generated the interrupt and the receiving module acts on the message packet to implement an interrupt handling routine depending on the identification of the peripheral device. According to another aspect, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts, and the receiving module generates a response packet containing that transaction identifier thereby allowing the peripheral device to monitor whether or not its interrupts have been treated properly.

Method and system for transmitting interrupts from a peripheral device to another device in a computer system

A cache system and method of operating are described in which a cache is connected between a processor and a main memory of a computer. The cache system includes a cache memory having a set of cache partitions. Each cache partition has a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor. The cache system also includes a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations in a cache partion wich depends on the address of said item in the main memory. This is achieved by a cache partition access table holding in association with addresses of items to be cached respective multi-bit partition indications identifying one or more cache partition into which the item is to be loaded.

Generation of a system model

A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis. This therefore increases the number of data values that can be held in relation to the number of addresses that can be identified by the second set of bit locations. A method of executing a succession of instructions in a computer system is also described.

System and method for addressing plurality of data values with a single

A computer system for executing branch instructions and a method of executing branch instructions are described. Tow instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

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Bath, United Kingdom

Andrew Craig Sturges