Nokia Mobile Phones Limited

Technophone Limited

Andrew Cooper

A maximum likelihood detector using the Viterbi algorithm for estimating a sequence of data bits received over a communication channel. Depending on the constraint length (C), a plurality of different states is associated with the transmitted bits (e.g. 16 if C=4). The detector comprises various data sources relating respectively to state transition probabilities (branch metrics, previous partial path metrics) and observed values of the received bits. Means are provided for calculating the partial path metrics for each state using values from said data sources. The calculating means comprise a common adder/accumulator for performing repeated additive arithmetic operations and for storing the cumulative result thereof. Multiplexing means are also provided for selectively coupling the data sources in a predetermined order to the adder/accumulator to implement the partial path metric calculation. The architecture is compatible with VLSI techniques and enables the detector to be implemented using minimal semiconductor area. The detector may be used independently as an equaliser or a decoder but in a preferred embodiment both these functions re-use the same common hardware in series enabling both the equaliser and decoder to be implemented in a single integrated circuit (i.e. on one `chip`).

Maximum likelihood sequence detector

A method of receiving data transmitted in a burst-mode radio communications such as GSM. Prior to transmission a set of first data elements (bits) relating to a first message which may be associated with a first channel type (e.g. a traffic channel (TCH) in GSM) has selected bits substituted or 'stolen' by data elements (bits) relating to a second message which may be associated with a second channel type (e.g. a fast associated channel FACCH in GSM). The data elements relating to the first and second messages are interleaved over the same or a different number of bursts. In a normal GSM traffic burst two single-bit flags are set to `1` to indicate respectively when the even bits or the odd bits of the burst have been stolen for FACCH data. A detector (5) is used to monitor the flags from the same number of bursts over which the FACCH is interleaved. In order to improve the chance of detecting a FACCH in noisy conditions a majority-vote circuit (9) is employed whereby a FACCH decode is initiated if the number of detected flags set to `1` exceeds a threshold value. Specifically, in the case of FACCH, the threshold value may be 5-8, i.e more than half the number of bursts over which the FACCH data is interleaved.

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Wokingham, United Kingdom

Andrew Cooper