Arm Limited

Andrew Christopher Rose

Richard Roy Grisenthwaite

Antony John Penton

Simon Andrew Ford

Vladimir Vasekin

Jason Parker

Simon John Craske

Dominic Hugo Symes

Matthew Lucien Evans

Peter Richard Greenhalgh

Paul Stanley Hughes

Stuart David Biles

Alex James Waugh

Edward Colles Nevill

David Raymond Lutz

Michael John Williams

David Michael Bull

Christopher Neal Hinds

Antony John Harris

Christopher Bentley Dornan

Hedley James Francis

David Kevin Hart

Andrew Brookfield Swaine

John Michael Horley

Bruce James Mathewson

Tessil Thomas

Krisztian Flautner

David James Seal

Ali Ghassan Saidi

Ian Rudolf Bratt

Stephen John Hill

Gareth Rhys Stockwell

Sheldon James Woodhouse

Ashley John Crawford

Allan John Skillman

Peter Guy Middleton

Timothy Charles Mace

Wilco Dijkstra

Daniel Adam Sara

Ashley Miles Stevens

Christopher William Laycock

Hakan Lars-Goran Persson

David John Butcher

Håkan Lars-Göran Persson

David John Gwilt

Anthony Jebson

Christopher Edwin Wrigley

Richard York

Sheshadri Kalkunte

Max Zardini

David Guillen Fandos

Javed Osmany

Donald Robert Sinclair

Andrew James Bolt

A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses. A descriptor table may be used to store process state identifiers, where the process states may include invalid, prepare and execute states. The processes may comprise a hypervisor and/or a virtual machine (VM).

Apparatus and method including an ownership table for indicating owner processes for blocks of physical addresses of a memory

A data processing apparatus () comprises address translation circuitry () to translate a first address into a physical address directly identifying a corresponding location in a data store, and a table () comprising one or more entries indexed by the physical address, wherein at least one of the entries specifies the first address from which the corresponding physical address was translated by the address translation circuitry ().

Apparatus and method for address translation and control of whether an access request is rejected based on an ownership table indicating an owner process for a block of physical addresses

A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.

Protected exception handling

A data processing system comprises ownership circuitry to enforce ownership rights of memory regions within a physical memory address space. A given memory region has a given owning process specified from among a plurality of processes and independently of privilege level. The given owning process has rights to control access to the given memory region. The given owning process designates the given memory region as one of: private to the given owning process and shared between the given owning process and at least one further source of memory access requests. A given owning process may deny access to the given memory region to a process having a greater level of privilege than the given owning process. Data stored within the given memory region may be destructively overwritten, and completion of the overwriting may be tracked by overwrite tracking hardware to ensure completion of the overwriting before the new owner obtains rights to control access.

Apparatus and method for sharing pages including enforcing ownership rights independently of privilege level

An apparatus and method are provided for handling write operations. The apparatus has a first processing device for executing a sequence of instructions, where the sequence comprises at least one instruction to activate a software protocol to establish an ownership right for writing data to a first memory region, and at least one write instruction executed following establishment of the ownership right, in order to perform one or more write operations to output write data for storage in at least one memory location within the first memory region. A writeback cache associated with the first processing device is used to store the write data output during the one or more write operations. Coherency circuitry is coupled to the writeback cache and to at least one further cache associated with at least one further processing device. The first processing device is responsive to a trigger event to initiate a clean operation in order to cause the write data to be written from the writeback cache to memory. Further, the coherency circuitry is responsive to the clean operation to interact with the at least one further cache to implement a hardware protocol in order to make the write data visible to the at least one further processing device. This can provide a very efficient and cost effective mechanism for implementing cache coherency in certain systems.

Apparatus and method for handling write operations

A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.

Secure initialisation

A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

Cache power management

Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.

Enforcing data protection in an interconnect

A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.

Invalidating stored address translations

An integrated circuit comprising multiple master units and multiple slave units connected via interconnect circuitry utilizes token based node-to-node communication flow management within the interconnect circuitry with a network node requesting a token and receiving a token signal before it asserts its communication signals onto a physical communication link shared between multiple virtual networks.

Communication using integrated circuit interconnect circuitry

A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.

Generation of trace data in a multi-processor system

In a data processing system, data representing program instructions is fetched from memory, each instruction being from one of a plurality of sets of instructions including at least first and second sets of instructions and each program instruction within the fetched data comprising one or more blocks to be pre-decoded, each block representing a portion of an instruction. Pre-decoding circuitry is configured to perform pre-decoding operations on the blocks. For at least one portion of an instruction from the first set of instructions and at least one portion of an instruction from the second set of instructions the pre-decoding operation performed on a block fetched from memory is independent of whether the block is identified as representing the at least one portion of an instruction from the first set of instructions or as the at least one portion of an instruction from the second set of instructions.

Reducing errors in pre-decode caches

A data processing apparatus and method are provided for handling hard errors occurring in a cache of the data processing apparatus. Cache location avoid storage is provided having at least one record, with each record being used to store a cache line identifier identifying a specific cache line. On detection of an error condition, one of the records in the cache location avoid storage is allocated to store the cache line identifier for the specific cache line associated with the entry for which the error condition was detected. A clean and invalidate operation is performed in respect of the specific cache line, and the access request is then re-performed. Cache access circuitry is arranged to exclude any specific cache line identified in the cache location avoid storage from a lookup procedure.

Handling of hard errors in a cache of a data processing apparatus

A multithreading processorinterleaves program instructions from different program threads to perform fine grained multithreading. Thread performance monitoring circuitrymonitors performance parameters of individual program threads to generate performance values. Issue control circuitryreads these performance values to determine which program thread is next selected to be active when a thread switch event occurs. The performance parameters measured may include the proportion of cycles in which a program thread is able to provide a program instruction for execution by the execution circuitrywithin the processor

Thread selection for multithreaded processing

A global interrupt number spaceis provided for use in message signalled interrupts. Interrupt destinationsare provided with pending interrupt cacheswith either backing storage provided by global pending status memoryshared by all the caches or separate individual pending status memories. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memoryduring the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

Communication of message signalled interrupts

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Cambridge, United Kingdom

Andrew Christopher Rose