National Instruments Corporation

National Instruments Coporation

Andrew C Thomson

Robert C Kowert

Brian Keith Odom

Aljosa Vrancic

Glen Sescila

Eric L Singer

Robert W Canik

David W Madden

William C Nowlin, Jr

Anita L Salmon

Jeff A Bergeron

Khasid Ali Khan

Daniel Liu

Mark Gruetzner

Michael G Jablin

C Paul Butler

Tian Shen

System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms.

Accumulation of waveform data using alternating memory banks

A system and method for communicating with a device over an external transmission medium. The system may include a host computer system, including a user application, a serial bus interface driver, and a first portion of an interface driver. The host computer may include a serial bus host controller. A serial bus may couple the serial bus host controller to a serial bus interface, which may include an interface connector adapted to couple to the device, wherein the serial bus interface may be operable to store and execute a second portion of the interface driver. When the user application generates an API function call, the first portion of the interface driver may generate a frame of interface commands that are transferred to the second portion of the interface driver for execution, thereby causing signals to be transmitted over an interface bus to the device.

System and method for providing a serial bus interface using distributed driver execution

A system and method for transferring data over a communications medium. A host is coupled to a device through a serial bus lacking error handling capabilities, such as an IEEE 1394 bus. The host may control the device by sending requests accessing its memory registers. The host generates a first request to the device to access a memory address location of the device, and which includes an address and status information indicating whether a prior request to the memory address location returned successfully. The device examines the status information to determine if it is a retry of a prior request, and if so, determines if the prior request completed successfully to the memory address location by comparing the address and data transfer size of the first request to those of the prior request. If identical, then the prior request completed successfully to the memory address location, and the request is ignored. Otherwise, the device retries the prior request. If the first request is not a retry the device performs it and returns an acknowledgement to the host indicating successful completion. If the host does not receive valid acknowledgement, it retries the first request, otherwise, it completes a transaction associated with the first request. Then, a new transaction request may be received which results in a new request being generated by the host to access the memory address location. The host may manipulate the status information in the new request to indicate that the first request to the memory address location returned successfully.

System and method for handling device retry requests on a communication medium

A system and method for GPIB autopolling of GPIB devices. A computer is coupled to one or more GPIB instruments through a GPIB to analyze, measure or control a process or unit under test. The computer includes a GPIB controller which monitors activity of the GPIB devices on the bus and produces heuristic information regarding the past behavior of the GPIB devices, such as a queue of one or more GPIB device IDs sorted by how recently each device was accessed. The heuristic information produced is stored on a memory and/or hard drive of the computer. A service request (SRQ) line assertion triggered by one or more GPIB devices may be received. The GPIB controller performs autopolling on the GPIB devices as ordered in the queue to determine which of the devices asserted the SRQ. If no queued devices asserted, the remainder of the devices are polled in arbitrary order.

GPIB system and method which performs autopolling using heuristics

An apparatus and method for write posting in a universal serial bus (USB) system includes a host computer connected to USB devices via a USB. The host computer generates requests to write data to memory within the USB device. The host computer includes a queue for posting the write requests on generation thereof. The write requests are posted in the queue until the host computer transmits a single data packet generated from the posted write requests. The Data packet is generated in response to the host computer generating a request to read data from the USB device, the host computer determining that the most recently posted write request is directed to a memory location within the USB device which is nonpostable, or an indication that the queue lacks storage space for subsequent write requests. The USB device receives the transmitted Data packet from the host computer and writes data to internal memory locations in accordance with the received Data packet.

System and method of write posting in a universal serial bus system

A device for configuring a serial ROM. In accordance thereto, a read instruction is serially transmitted to the input of the serial ROM. Thereafter, an x-bit address of all zeros is serially transmitted to the input of the serial ROM. Each bit of the instruction and x-bit address is transmitted to the input of this serial ROM on a rising edge of a clock also inputted to the serial ROM. The output of the serial ROM is connected to a precharged sense node. Prior to the serial ROM outputting data in response to the x-bit address, the serial ROM will discharge the sense node to ground if the serial ROM is one of the first type of serial ROMs. However, if the serial ROM is a second type, the sensing node will not be discharged to ground prior to output of the data. Immediately after transmission of the x-bit address, a configuration register is set to indicate the type of serial ROM. In this regard, the configuration register is set according to whether the sense node is discharged or not upon complete transmission of the x-bit address.

Auto configuration of a serial ROM by sensing an output of the serial

An apparatus and method is provided for caching data in a universal serial bus (USB) system. In one embodiment, the present invention employs a host computer coupled to an I/O device via a USB. The host computer includes a data cache for storing data retrieved from the I/O device. The data cache allows data to be returned to the host computer upon request without accessing the I/O device via a USB transaction. A cacheability look-up table and cache table are provided to ensure the integrity of data returned to the host computer. Requested data is returned from the I/O device if the cacheability look-up table indicates the requested data is noncacheable. Data is returned from the data cache if the cache table indicates the requested data is available in the cache as valid data. If the cache table indicates the requested data is not available in the cache as valid data, the requested data is returned from the I/O device along with data stored in predetermined I/O device addresses. The additional data is stored in the cache for subsequent access by the host computer. By returning data from the cache, the present invention reduces the response time and reduces the traffic over the USB between the host computer and I/O device.

Method for caching data and generating only one read request to read the

A GPIB system for capturing GPIB signals at a predetermined rate and upon valid transitions of the data valid signal. A first sampling circuit samples the GPIB at the predetermined rate and a second sampling circuit samples the GPIB with transitions of the data valid signal. Capture logic preferably includes data valid logic for monitoring the data valid signal to assure valid transitions. The capture logic also preferably includes select logic for selecting between the GPIB signals sampled at the predetermined rate and upon assertion of the data valid signal, where data valid signal transitions preferably have higher priority. The capture logic monitors the sampled GPIB signals and the data valid logic to enable a first-in, first-out buffer to capture sampled data upon predetermined capture conditions and upon transitions of the data valid signal. In this manner, data signal transitions which might otherwise be missed by the predetermined sampling rate are sampled and captured. Furthermore, a counter circuit is implemented to provide a time-stamp value into the buffer after each captured data value. The capture logic asserts a time-stamp signal to select the time-stamp value and also enables the buffer to capture time-stamp value into the buffer.

Bus analyzer for capturing bus signals at a predetermined rate and upon

A deglitch circuit for filtering false transitions of an input signal based on transitions of a clock signal. A plurality of memory devices as provided for detecting the input signal being assay for two, three and five transitions of the clock signal in the preferred embodiment. Programmable select logic is also provided for selecting between these three cases. In the preferred embodiment, six separate flip-flops are included and clocked by the clocked signal, four of the flip-flops being reset upon spurious negations of the input signal for reign such transitions, and where two of the four flip-flops are clocked on the rising edge whereas the other two are clocked on the falling edge of the clock signal. The programmable select logic preferably includes a multiplexer for choosing between the three cases. In the preferred embodiment, the input signal is the data valid (DAV) signal of a GPIB, where the deglitch circuit assures valid data sampling on a GPIB.

Deglitch method and apparatus to assure valid data sampling

A GPIB bus extender which intelligently supports the IEEE 488.2 find listeners protocol. The GPIB bus extender of the present invention monitors the bus and determines when a talker is present on the bus. When the GPIB extender detects a talker present on the bus, the extender configures itself as a listener to receive any messages for devices on the remote bus. When the GPIB extender does not detect a talker present on the bus, the extender does not configure itself as a listener, but rather is prepared to participate in a find listener protocol.

GPIB extender with find listener protocol capabilities

A modified IEEE 488.1 bus interface increases, by as much as a factor of eight, the rate at which inter-instrument data transfers can be performed. The bus interface state machines presented in the ANSI/IEEE Std 488.1-1987 have been modified so that if all the devices involved in a particular data transfer are equipped to handle high speed data transfers, then a modified data transmission methodology is used so as to enable multiline messages to be transmitted at a higher speed than would otherwise be possible. If any of the devices involved in a particular data transfer does not have an interface equipped to handle high speed data transfers, this condition is automatically detected by the interfaces with high speed capability, and then the standard data transmission methodology is used. The high speed data transmission mode is totally transparent to the controller software in that it does not require any changes to the controller software nor to the device drivers and device application programs.

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Austin, TX, United States of America

Andrew C Thomson