Other

Staktek Group L.p.

Dense-pac Microsystems, Inc.

Dpac Technologies Corp.

Stuktek Group L.p.

Andrew C Ross

Glen E Roeters

Harlan R Isaak

Techniques for sterilizing a fomite are disclosed. A UV sterilization apparatus includes a housing for enveloping a fomite inside the housing. The housing is composed of a material that prevents transmission of electromagnetic radiation in the ultraviolet range. Attached to the housing is a closure element, and the closure element is also composed of a material that prevents transmission of electromagnetic radiation in the UV range but allows transmission of electromagnetic radiation in the visual range. An ultraviolet light source is attached to an internal surface of the housing or an internal surface of the closure element, and the light source sterilizes the fomite enclosed inside the housing by transmitting ultraviolet electromagnetic radiation towards the fomite.

UV sterilization of user interface fomites

A chip stack comprising a flex circuit including a flex substrate having a first conductive pattern disposed thereon and a plurality of leads extending therefrom. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may be electrically connected to the first conductive pattern of the flex circuit such that the integrated circuit chip packages are positioned upon respective ones of opposed top and bottom surfaces of the flex substrate. Alternatively, one of the integrated circuit chip packages may be positioned upon the top surface of the flex substrate and electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached in a non-conductive manner to the bottom surface of the flex substrate such that the conductive contacts of such integrated circuit chip package and the leads collectively define a composite footprint for the chip stack.

Stacking system and method

CSP chip stack with flex circuit

A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame. Alternatively, one of the integrated circuit chip packages may be electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached to the base substrate and at least partially circumvented by the interconnect frame such that the circumvented integrated circuit chip package and the second conductive pattern of the interconnect frame collectively define a composite footprint for the chip stack. A transposer layer may be included as a portion of each chip stack, with the transposer layer including a third conductive pattern specifically configured to provide a CSP-TSOP interface.

Panel stacking of BGA devices to form three-dimensional modules

A stackable integrated circuit chip package comprising an interconnect sub-assembly which includes an interconnect substrate having first, second and third conductive pad arrays disposed thereon. The interconnect sub-assembly also includes a first rail member which is attached to the interconnect substrate and has a fourth conductive pad array disposed thereon, and a second rail member which is also attached to the interconnect substrate and has a fifth conductive pad array disposed thereon. The fourth and fifth conductive pad arrays are electrically connected to respective ones of the second and third conductive pad arrays of the interconnect substrate. In addition to the interconnect sub-assembly, the chip package of the present invention includes an integrated circuit chip which is electrically connected to the first conductive pad array of the interconnect substrate of the interconnect sub-assembly.

CSP stacking technology using rigid/flex construction

A chip module comprising a chip array which includes an interconnect substrate having opposed, generally planar surfaces and a first interconnect pad array disposed on at least one of the surfaces thereof. Attached to the interconnect substrate is at least one integrated circuit chip of the chip array which is electrically connected to the first interconnect pad array. The chip module further comprises a package which itself comprises a main body defining a cavity sized and configured to receive the chip array and having a generally planar interconnect shelf which extends within the cavity and includes a second interconnect pad array disposed thereon. The package also includes a lid which is attachable to the main body. The chip array is insertable into the cavity such that the first and second interconnect pad arrays are in aligned contact with each other and the attachment of the lid to the main body encloses and seals the chip array within the package.

Growing community of inventors

Ramona, CA, United States of America

Andrew C Ross