Gazelle Microcircuits, Inc.

Triquint Semiconductor Corporation

Andrew C Graham

Mark E Fitzpatrick

David C MacMillan

Robert C Burd

Wei Chen

Gary R Gouldsberry

Michael G France

Dung Q Tran

Richard J Kelly

A circuit is which, when used in a voltage controlled oscillator (VCO) circuit, detects a frequency on the output of the VCO and, if this output frequency is above a certain value, the circuit forces the output frequency of the VCO to decrease until it is below the certain value. This acts to keep the output frequency of the VCO below a selected frequency which can be accurately processed by the feedback circuits driven by the VCO. Once the output frequency of the VCO is below the certain value, the circuit stops forcing the output frequency to decrease, and the circuit becomes transparent. At this point, the conventional feedback circuitry driving the VCO takes over the adjustment of the VCO output frequency.

Circuit for limiting maximum frequency output of a voltage controlled

A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

Logic array having high frequency internal clocking

In accordance with the invention, a circuit and a method for extracting a clock signal from a serial data stream are provided. A window pulse is generated such that transitions of a delayed version of the serial data stream occur near the center of the window pulse. A PUP signal and a PDN signal are generated having pulse widths indicative of the time at which transitions of the clock signal occur with respect to the window pulse. The PUP and PDN signals are used to generate a reference voltage to control the clock frequency. Window pulses may be generated in response to only positive transitions or to only negative transitions of the delayed serial data stream, or alternatively may be generated in response to both negative and positive transistions. The amount of delay introduced to the serial data stream may be selectively adjusted for different bit rates.

Circuit and method for extracting clock signal from a serial data stream

In one embodiment, the threshold voltage of the electrostatic protection circuit is selectively raised above the power supply voltage by the inclusion of a plurality of serially connected diodes connected between the power supply voltage and a discharge reference rail. The serially connected diodes become forward biased when a voltage applied to the rail is above the power supply voltage by a voltage equal to the sum of the various voltage drops across the serially connected diodes. The various input pads of the integrated circuit are connected to an anode of an associated diode, wherein the cathode of the associated diode is connected to the discharge reference rail, rather than directly to V.sub.DD as in the prior art. The anodes of each of these diodes are also connected to the device to be protected within the integrated circuit. Thus, when a voltage applied to the input pad is approximately one diode drop above the discharge reference rail, the voltage at the input pad will be shunted to the power supply voltage generator through the serially connected diodes.

Structure for providing electrostatic discharge protection

A phase-locked loop responsive to both phase and frequency difference between the incoming signal and the feedback signal is provided. Using a reference signal, this phase-locked loop accepts a wide range of frequencies similar to a phase-locked loop having a phase frequency detector, and also achieves the noise performance of a phase-locked loop having only a simple phase detector. In one embodiment, the phase-locked loop is a combination including first and second phase-locked loops. The reference signal is provided to the first phase-locked loop, which includes a phase frequency detector. This first phase-locked loop is used to control a second phase-locked loop, which includes a phase detector. A voltage clamp can also be provided to enhance the ability to lock a signal among several signals, or from a noisy background.

Phase-locked loop with clamped voltage-controlled oscillator

This invention discloses an integrated circuit implemented in compound semiconductor technology including an input signal lead and an output signal lead, and buffer circuitry interconnecting those leads, the circuit being compatible with standard logic signals thereinto and therefrom.

Compound semiconductor integrated circuit compatible standard logic

This invention discloses a push pull logic circuit which includes a capacitor connected to the output signal lead of the circuit, and also a plurality of diodes, in parallel with the capacitor and connected to the output signal lead.

Capacitor coupled push pull logic circuit

This invention discloses a logic circuit including first, second and third transistors with the control terminals of two of those transistors being connected to the input signal lead, with the output signal lead being connected to one of the current handling terminals of one of those transistors, and with a load device connected to the respective current handling terminals of those two transistors and one of the voltage supply terminals.

Logic circuit connecting input and output signal lines

A programmable array including FET devices arranged in rows and columns is disclosed in which first and second bit lines for cells in adjacent first and second columns are arranged so that a fusible link connecting a cell of a column to its associated bit line crosses the bit line associated with the adjacent column of cells. By doing so, two fuses may now be located in an area which was heretofore occupied by a single fuse.

Semiconductor fuse programmable array structure

This invention discloses a laser programmable read only semiconductor-based memory array comprised of memory cells, a group of word lines, a group of bit lines. Each of the memory cells is connected to one of the group of bit lines, and one of the group of word lines and each memory cell is comprised of a memory element and a laser programmable link. In one embodiment, each memory cell is comprised of a transistor and a laser programmable link composed of the same material as either the word or the bit lines. Programming is accomplished by laser coding of the links.

Laser programmable memory array

This invention discloses an oscillator circuit wholly contained in a single integrated circuit and implemented in compound semiconductor technology, wherein the oscillation frequency thereof is substantially stable over variations in supply voltage, process variations in fabrication, and temperature.

Oscillator circuit

Semiconductor integrated circuit compatible with compound standard logic

Logic circuit connecting input and output signal leads

This invention discloses a TTL compatible output buffer circuit which provides that in the state where the output signal thereof is high, no substantial current is provided inward of the buffer circuit from the output signal lead over a wide range of voltages applied to the output signal lead, including applied voltages substantially greater than that supplied by the voltage supply terminals of the circuit, with the circuit being further implemented in compound semiconductor technology.

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Sunnyvale, CA, United States of America

Andrew C Graham