Harris Corporation

Andrew C Barber

Michael Suchoff

A signal processing arrangement adjusts baud timing in a communication system receiver, wherein an information signal comprised of (sin(x))/x function contributions of successively adjacent bits is received via a memoryless channel. The information signal is sampled in accordance with a baud sampling clock signal, to derive successive samples of bits contained in the information signal. The sampling clock signal has a baud sampling clock frequency that is adjusted by a phase locked loop in accordance with a timing error signal. The signal processing arrangement comprises an intersymbol interference (ISI) correlation-driven baud timing recovery scheme which makes use of the fact that, for a given bit, at all instances in time other than where its peak occurs, the channel will contain energy from adjacent bits, so that there will be a substantial correlation of channel energy among successively adjacent bits of a transmitted sequence. On the other hand, for baud timing accurately at the peak of a given bit, none of the energy of any other bit will contribute to the energy at that baud time. The timing error signal is based upon ISI-correlation of adjacent bits.

Method and apparatus for recovering baud timing from correlation of

A linearized voltage controlled amplifier (VCA) circuit uses the resistance of a gain control MOSFET to control amplifier gain in accordance with a DC gain control voltage. A gain control voltage is applied to the gain control MOSFET's gate through a gate input resistor that forms a voltage divider with a feedback resistor from the output of the amplifier. Since the VCA's output terminal is a low impedance node, the voltage divider network applies most of the gain control voltage to the gate of the gain control MOSFET. Conversely, a small fraction of the amplifier output signal is coupled to the gain control MOSFET's gate, to reduce distortion. The linearized VCA circuit is augmented by a gate drive correction circuit, through which the gain control voltage is coupled to the VCA's gain control MOSFET. The gate drive correction circuit is comprised of a difference amplifier and a compensating MOSFET that is matched with the gain control MOSFET of the VCA circuit for controlling its gate drive voltage.

Linearization of voltage-controlled amplifier using MOSFET gain control

A reduced hardware complexity, reduced computational intensity finite impulse response filter architecture for filtering multiple (quadrature) channels of an RF modem comprises a cascaded arrangement of L data register stages through which respective digitally encoded data sample values of a signal to be filtered are sequentially clocked. Each data register stage has a data capacity greater than twice the code width of a respective digitized channel sample, so that each register stage can store both I and Q channel data. A multiplier unit is coupled to the data register and multiplies both I and Q contents of respective ones of the register stages by respective impulse response coefficient values. The resulting I and Q products are summed into I and Q channel convolutional sums.

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Venice, CA, United States of America

Andrew C Barber