Arm Limited

Andrew Burdass

Isidoros Sideris

Daren Croxford

Patrick Gerard McGlew

Andreas Due Engh-Halstvedt

David James Seal

Sean Tristram Ellis

Roko Grubisic

Nebojsa Makljenovic

Kenneth Edvard Ostby

Simon Alex Charles

Michel Patrick Gabriel Emil Iwaniec

David Kevin Hart

A graphics processing unit is operable to execute graphics processing programs comprising sequences of instructions to perform graphics processing operations. The graphics processing unit includes execution processing circuitry operable to execute instructions to perform graphics processing operations and instruction issuing circuitry operable to issue instructions to be executed to the execution processing circuitry. The graphics processing unit also includes energy management circuitry operable to monitor the energy usage by the execution processing circuitry when executing instructions, determine, based on the monitoring of the energy usage, a permitted energy usage range for the execution processing circuitry when executing instructions for a future time period, and control the issuing of instructions to the execution processing circuitry by the instruction issuing circuitry during the future time period based on the permitted energy usage range determined for the future time period.

Energy management in graphics processing units

A data processing apparatus has control circuitry for detecting whether a first micro-operation to be processed by a first processing lane would give the same result as a second micro-operation processed by a second processing lane. If they would give the same result, then the first micro-operation is prevented from being processed by the first processing lane and the result of the second micro-operation is output as the result of the first micro-operation. This avoids duplication of processing, to save energy for example.

Preventing duplicate execution by sharing a result between different processing lanes assigned micro-operations that generate the same result

A graphics processing apparatus and method of performing graphics processing are provided. The graphics processing apparatus comprises a sequence of processing stages capable of performing graphics processing to generate a frame of display data. The graphics processing is performed on a tile-by-tile basis. The graphics processing apparatus is capable of determining if a current tile subject to the graphics processing is empty. At least one processing stage of the sequence of processing stages is omitted for graphics processing of the current tile in dependence on whether the current tile is empty.

Tile based graphics processor and a method of performing graphics processing in a tile based graphics processor

A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by processing circuitry is for the same data processing operation and specifies the same at least one operand as the last valid micro-operation processed by the processing circuitry. If so, then the control circuitry prevents the processing circuitry processing the current micro-operation so that an output register is not updated in response to the current micro-operation, and outputs the current value stored in the output register as the result of the current micro-operation. This allows power consumption to be reduced or performance to be improved by not repeating the same computation.

Reuse of results of back-to-back micro-operations

A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by a processing pipeline would give the same result as an earlier micro-operation. If so, then the current micro-operation is passed through the processing pipeline, with at least one pipeline stage passed by the current micro-operation being placed in a power saving state during a processing cycle in which the current micro-operation is at that pipeline stage. The result of the earlier micro-operation is then output as a result of said current micro-operation. This allows power consumption to be reduced by not repeating the same computation.

Power saving by reusing results of identical micro-operations

Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

Address translation in a data processing apparatus

A single instruction multiple data processing pipelinefor processing floating point operands includes shared special case handling circuitryfor performing any operand dependent special case processing operations. The operand dependent special case processing operations result from special case conditions such as operands that are denormal, an infinity, a not-a-number and a floating point number requiring format conversion. The pipelinemay in some embodiments be stalled while the operands requiring special case processing are serially shifted to and from the shared special case handling circuitry. In other embodiments the instruction in which the special case condition for an operand arose may be recirculated through the pipeline with permutation circuitrybeing used to swap the operands between lanes in order to place the operand(s) requiring special case processing operations into the lane containing the shared special case handling circuitry

Operand special case handling for multi-lane processing

A data processor comprising: a control register operable to store a cache control value; and data accessing logic responsive to a data access instruction and to said cache control value to look for data to be accessed in a cache if said cache control value has a predetermined value and not to look for said data to be accessed in said cache if said cache control value does not have said predetermined value.

Control of data accesses to a cache in data processing

A processor coreis provided with an interrupt controllerwhich serves to set an interrupt mask bit F and a hardware control when an interrupt fiq occurs. A masking control signal NMI serves to either allow or prevent the software clearing of the interrupt mask bit F.

Interrupt masking control

An integrated circuit processor coreis provided with an instruction pipelinealong which program instructions advance. When an exception condition occurs part way through execution of a particular program instruction, then a prefetch of the exception handling program instruction corresponding to that exception is initiated before the currently executing program instruction has completed. In this way the exception handling program instruction is more rapidly available to start the exception processing. The early prefetch may involve performing a lookup in a cache memoryand any necessary linefill upon a miss. In addition, the exception handling program instruction amy also be fed into the instruction pipelinebefore an instruction boundary is reached.

Prefetching exception vectors by early lookup exception vectors within a cache memory

A cache memory includes error bits corresponding to each line of data. An error detecting circuit uses these error bits to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.

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Cambridge, United Kingdom

Andrew Burdass