Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Compaq Computer Corporation, Inc.

Andrew Brown

Andrew C Cartes

Peter A Hansen

David F Heinrich

Christopher J Frantz

Kevin B Leigh

Theodore F Emerson

Darren John Cepulis

E David Neufeld

Kevin G Depew

Paul R Culley

Jeffrey R Hilland

Daniel Nathan Cripe

Kevin Mark Jones

Stephen M Zaudtke

Douglas R Hascall

Gordon M Barton

Michael F Angelo

Gary W Thome

Vincent Hung Nguyen

Suhas Shivanna

Dwight L Barron

Patrick A Raymond

Justin E York

Luis E Luciani, Jr

Chanh V Hua

Jeffrey S Autor

Robert L Noonan

Michael R Garrett

Erin Antony Handgen

Michael C Sanders

Bryan E Stiekes

James T Bodner

Thomas D Rhodes

John Harsany

Alan M Green

Gerald K Kleyn

David Kimler Altobelli

Jeff D Pipkins

Mohammed Saleem

Donnie G Wahlquist

John R Carpenter

David E Neufeld

Paul W Hoke

Sreenivasakumar Sivasubramanian

Leopoldo Alaniz

Doug Hascall

Andrew L Fisher

Luis Luciani

For computing nodes having a first programmable and comprising a first node and a second node, an update of the first node from the first programmable to a second programmable across an external network is initiated. In response to the update being interrupted, the first programmable is automatically reinstated on the first node by retrieving the first programmable from the second node across an internal network. The second node is automatically updated to the second programmable by retrieving the second programmable from the first node across the internal network in response to completion of the update of the first node to the second programmable.

Update of programmable for computing nodes

An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Serial connection between management controller and microcontroller

Examples disclosed herein relate to securing a controller of a device. The controller is to determine whether a network interface of the device is connected to the Internet. Communications are restricted on the network interface in response to the port having access to the Internet. In some examples, the restriction can be related to a vulnerability.

Restrict communications to device based on internet access

Various examples described herein provide for causing operation of a cooling system of a computing device to be adjusted (e.g., reduced or disabled) during at least a portion of a backup operation, where data is copied from volatile memory of the computing device to non-volatile memory of the computing device. Some examples can be implemented with respect to a type 10 (T10) non-volatile dynamic inline memory module (NVDIMM) configuration.

Responding to data backup operation

Techniques to inspect packets to determine a destination node are provided. In one aspect, a Wake on Lan (WOL) packet may be received at a switch. A destination node of the WOL packet may be determined. An indication of the determined destination node may be sent to a management controller. The management controller may cause the destination node to awaken.

Packet inspection to determine destination node

Data requests for data stored in a non-volatile media may be monitored and used to identify if the media is being used as memory or storage. The accessibility of the data may be modified based on the identified usage model.

Modifying accessibility based on memory access patterns

Systems and methods are provided for agentless error management by an agentless system. The agentless system can include a management processor and a memory that stores agentless management firmware. Execution of the firmware causes to obtain first graphic data corresponding to actual output graphics that are displayed via a display device. An error is detected in the actual output graphics. The error can indicate one or more differences between the actual output graphics and intended output graphics. The detected error can be addressed, such that it is remedied or attempted to be remedied by eliminating the differences and/or extraneous graphical content from the displayed data or actual output graphics.

Systems and methods for agentless error management

Example implementations relate to a server including a platform controller hub (PCH), where the PCH includes a peripheral device manager, a management processor coupled to the peripheral device manager, and a peripheral device interface to couple with a peripheral device and provide out of band access of the peripheral device via the management processor and peripheral device manager to a memory of the server.

Peripheral device server access

A method for disabling counterfeit cartridge operation is provided. The method includes detecting a cartridge in a blade enclosure. The method includes checking authentication credentials of the cartridge. The method includes determining the cartridge to be counterfeit. The method includes disabling the cartridge in response to determining the cartridge to be counterfeit.

Disabling counterfeit cartridges

Techniques for determining an address of a management controller are provided. A microcontroller on a cartridge may read a signal from an enclosure, wherein the signal is associated with a slot in the enclosure. A network address for a first management controller associated with the cartridge may be determined based on the signal. The first management controller may be communicated with for cartridge management actions.

Slot based management controller address

One embodiment is a method that segments a bus topology to increase addressable devices that can attach to a bus. Switching occurs between different segments on the bus having multiple bus segments linked together.

Segmenting bus topology

A hardware enablement apparatus includes a processor, and a communications interface configured for writing license data to one or more data registers and for using the license data to selectively enable, under control of the processor, hardware features associated with the data registers, at least one of the data registers being implemented in non-volatile memory.

Hardware enablement using an interface

Growing community of inventors

Houston, TX, United States of America

Andrew Brown