Maxtor Corporation

Seagate Technology Incorporated

Linear Technology Corporation

Analog Devices International Unlimited Company

Andrew Bishop

Robert C Dobkin

Russell W Brown

Gregg R Castellucci

Thomas P Hack

Ivan Chan

Eduardo Gentile Veiga

Benjamin Thomas Voegeli

Jeffrey David Marvin

Alfonso Centuori

The subject disclosure describes a structure and method that generates the average of two or more reference quantities (e.g., reference voltage potentials) and monitors the integrity of the voltage reference potentials. The subject technology produces a reference with improved accuracy and more accurate monitoring compared to traditional techniques. For example, the subject technology provides for a fault circuit that includes a monitoring circuit, and an averaging circuit configured to receive a plurality of reference signals and to produce an averaged reference signal based on the received plurality of reference signals. In some examples, the monitoring circuit is configured to receive the averaged reference signal from the averaging circuit, compare the averaged reference signal to each of the plurality of reference signals, and generate a fault signal when the averaged reference signal deviates from at least one of the plurality of reference signals by at least a threshold value.

Averaged reference with fault monitoring

Apparatus is configured for producing an output signal indicating an operating status of a monitored circuit. An input signal relating to the monitored circuit is received at an input node. A pulse train generator, coupled to the input node, is configured for generating a pulse train of a prescribed repetition rate at a duty cycle alternated between first and second duty cycle values at a prescribed frequency. The duty cycle and frequency are indicative of operating status of the monitored circuit.

Apparatus and method for producing signal conveying circuit status information

A read/write device for a disk drive is disclosed. The read/write device includes a pre-amplifier and a recording head. The read/write device also includes a write signal path between the pre-amplifier and the recording head. The write signal path includes a write current. The read/write device also includes a read signal path between the pre-amplifier and the recording head. The read signal path includes an induced current related to the write current. The read/write device also includes a shunt path in the pre-amplifier to draw a part of the induced current from the read signal path.

Device for limiting current in a sensor

The high frequency components of a SCSI signal are adaptively equalized using an adaptive filter having an adjustable gain. A comparator is used to compare an input signal with a predetermined threshold level. Based on the result of the comparison, the adjustable gain of the adaptive filter is modified.

Mixed signal adaptive boost equalization apparatus and method

A technique and associated circuitry are provided for measuring a buffered write head voltage, and measurement of thin-film write head DC head voltage in a disk-drive, along with a procedure for calibrating/optimizing the write current amplitude based on the measurement of the buffered write head voltage. A write driver includes a terminating resistor, coupled to the write element of a transducer head in a disk drive, wherein controlling the write current of the write driver includes the steps of measuring the resistance R of the terminating resistor; measuring the resistance R of the write element; and generating the write current amplitude based on the resistances R and R .

Method and apparatus for controlling write current in writer drivers

An all digital timing loop is employed in a hard disk drive read channel for improved timing performance. Synchronizing the read channel to a sinewave preamble pattern at the beginning of a servo or data read operation is accomplished by first determining an accurate initial estimate of phase angle, and loading that phase value into the digital phase lock loop phase interpolator without having to halt and restart the sample clock. The timing loop synchronizes to the preamble input pattern very quickly so that timing overhead is reduced. The initial phase estimate is formed by accumulating even and odd ADC samples over a selected integration period, and using those values to access an arctan lookup table. Since ratios of even and odd ADC samples are used, gain variations and other analog tolerance issues are avoided.

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Essex, VT, United States of America

Andrew Bishop