International Business Machines Corporation

Freescale Semiconductor,inc.

Andrew Augustus Bjorksten

Ruchir Puri

Thomas Edward Rosser

Martin Stanley Schmookler

Donald George Mikan, Jr

Iris M Plaxton

Brian Allan Zoric

Samuel J Rauch

John H Osman

Jason M Bennett

Christopher McCall Durham

Paul Gerard Villarrubia

Michael Kevin Ciraula

James Edward Phillips

Khoi Mai

Ramesh Chandra Agarwal

Paul C Rossbach

Richard E Fry

Freg G Gustavson

Duc Quang Bui

A device () receives new program files () and uses pre-internalized images to avoid having to internalize a program file every time that program execution occurs. In one embodiment, a software Virtual Machine () in the device functions to implement the pre-internalization. Once the program files are pre-internalized to create images that are stored in a permanent memory () of the device, the images may subsequently be executed without having to perform a pre-internalization operation. Additionally, use of dynamic memory () is reduced in connection with subsequent program execution and execution time of new program files is reduced.

Method and device for creating and using pre-internalized program files

A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.

Logic circuitry

A certain type of gates, such as NOT gates, in a logic network are moved to the network boundary (i.e., inputs or outputs), at least in part, by selecting nodes in the network as candidate nodes for choosing among to determine output phase assignments. Such a candidate node is selected in response to non-reconvergence of branches fanning out from the node.

Identifying candidate nodes for phase assignment in a logic network

At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to 'reconvergent fanout nodes'. A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.

Identifying an optimizable logic region in a logic network

A system and method are provided for distributing clock signals within integrated circuitry. The system includes a number of cells for the integrated circuitry such that the cells include substantially horizontal regions within which are disposed substantially horizontal lines representative of a first clock. The cells also include substantially vertical regions within which are disposed vertical lines representative of a second clock. The cells are disposed in substantially horizontal layers. The vertical regions, including the vertical lines representative of a second clock are substantially vertically aligned. The cells include circuitry disposed within each cell such that a first portion of such circuitry includes signal wiring, and a second portion of such circuitry includes clock wiring, and such that the disposition of said circuitry minimizes a cumulative length of signal wiring and clock wiring.

Multi-phase clock distribution method and system for complex

A method and system are described, which utilize timing analysis to verify a digital circuit design that includes a plurality of dynamic logic circuit cells employing diverse circuit techniques and that may also include static logic circuit cells. For each dynamic circuit cell, a set of timing constraints is defined based upon the circuit technique employed by the associated dynamic logic circuit cell. Each timing constraint prevents a possible mode of failure of the associated dynamic logic circuit cell. The digital circuit design is then verified. The verification includes a determination of whether or not each dynamic logic circuit cell satisfies its respective set of timing constraints while connected to the other circuit cells. In an embodiment in which the digital circuit design includes a static logic circuit cell, the verification includes a verification that the static logic circuit cell has a correct inversion relationship between its input and output.

Method and system for verifying a digital circuit design including

In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.

Selecting phase assignments for candidate nodes in a logic network

A method and implementing structure for a domino block circuit 200 includes a minimal component latching circuit 203 which is merged with an exemplary MUX functional block 201, to provide both inverting and latching functions with minimal propagation delay in the domino data path. Implementations with scanning circuitry and including a holding feature are also illustrated.

Latch structure for ripple domino logic

A method and system for interchanging operands and loading such operands into a plurality of operand registers in an execution unit with the data processing system during execution of a complex instruction. A plurality of operands are stored within a register file, including a first operand and a second operand. An instruction is loaded into the first stage of the execution pipe within the execution unit, wherein the instruction has a plurality of fields. Such fields include a first and second field, containing a first and second operand pointer, respectively, for designating a value stored in the register file for loading into first and second operand registers, respectively. Next, the first and second operand pointers are interchanged between the first and second fields. Finally, the first operand register is loaded with the value in the register file designated by the second operand pointer stored in the first field, and the second operand register is loaded with the value in the register file designated by the first operand pointer in the second field, wherein the values in the register file designated by operand pointers in the fields of the instruction are loaded into different operand registers than originally specified by the instruction, thereby facilitating execution of a complex instruction in the execution unit.

Method and system for interchanging operands during complex instruction

A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the position of the most significant bit of the unaligned result that is set, when a normalized result is required, and that produces a shift alignment vector indicating the position of a bit of the unaligned result having the weight of a minimum allowable exponent for a given format, when a denormalized result is required. A shift register responsive to the alignment circuit shifts the unaligned result by the number of bits indicated by the shift alignment vector. The bit of the unaligned result having the weight of the minimum allowable exponent for the given format is determined by subtracting the binary value of the minimum allowable exponent from the binary value of the most significant bit of the unaligned result, wherein the difference indicates the number of bits from the most significant bit that the bit having the weight of the minimum allowable exponent is positioned.

Fast floating point result alignment apparatus

A method and system for performing floating-point division of a dividend by a divisor within a floating-point unit having multiply and add functions are disclosed. In performing floating-point division, a quotient having a mantissa is produced. The method uses an approximation based on a linear approximation stored within a first table. The first approximation approximates two divided by the divisor. A second table value is also selected from the table lookup. The second table value approximates the reciprocal of the divisor squared. Both the first and second table values operate as linear correction terms. Also according to the present invention, a method and system are disclosed that perform an early exit check during the division operation to confirm whether the resultant quotient has an acceptable accuracy and if the accuracy is unacceptable, then perform a rounding correction based upon a given rounding boundary.

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Austin, TX, United States of America

Andrew Augustus Bjorksten