Lattice Semiconductor Corporation

Andrew Armitage

Bradley Felton

Om P Agrawal

Satwant Singh

Chan-Chi Jason Cheng

Jason Cheng

Paul R Bonwick

A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.

Programmable logic device with flexible memory allocation and routing

A memory provides a programmable write port data width and an independently programmable read port data width. The independence between the programmable write port data width and the programmable read port data width is achieved without the use of a third clock domain.

FIFO memory with programmable data port widths

Growing community of inventors

Corsham, United Kingdom

Andrew Armitage